T. Okuda

DRAM Using Crystalline Oxide Semiconductor for Access Transistors and Not Requiring Refresh for More Than Ten Days

H. Inoue, T. Saito, T. Onuki, 2012, 2012 4th IEEE International Memory Workshop.

A 250 Mb/s 1 Gb double data rate SDRAM with a bi-directional delay and an inter-bank shared redundancy scheme

Y. Takai, M. Fujita, H. Ohkubo, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A 12 ns 8 MB DRAM secondary cache for a 64 b microprocessor

I. Naritake, M. Togo, T. Sugibayashi, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A 1 Gb DRAM for file applications

I. Naritake, T. Murotani, T. Sugibayashi, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

SP 23.4: A 2.511s Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay

Toshiro Itani, Haruo Iwasaki, Takanori Saeki, 1995 .

A 30 ns 64 Mb DRAM with built-in self-test and repair function

N. Kasai, M. Takada, A. Tanabe, 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.