Pascal Gouraud

发表

Cleaning chamber walls after ITO plasma etching process

Salma Younesy, C. Petit-Etienne, Sébastien Barnola, 2020, Advanced Lithography.

Effect of etch pattern transfer on local overlay (OVL) margin in 28nm gate integration.

Erwine Pargon, Pascal Gouraud, Bertrand Le-Gratiet, 2014, Advanced Lithography.

Comparison between organic spin-on BARC and carbon-containing CVD stack for 65-nm gate patterning

Jean-Damien Chapon, Jerome Belledent, Yorick Trouiller, 2005, SPIE Advanced Lithography.

Comparison of physical gate-CD with in-die at-speed non-contact measurements for bin-yield and process optimization

Mario M. Pelella, Pascal Gouraud, G. Johnson, 2009, Advanced Lithography.

Plasma treatments to improve line-width roughness during gate patterning

Olivier Joubert, Marc Fouchier, Erwine Pargon, 2013 .

Plasma treatment to improve linewidth roughness during gate patterning

Olivier Joubert, Marc Fouchier, Erwine Pargon, 2012, Advanced Lithography.

Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution

C. Laviron, Stephane Monfray, Claire Fenouillet-Beranger, 2009, ESSDERC 2009.

Ultra-Thin (4nm) Gate-All-Around CMOS devices with High-k/Metal for Low Power Multimedia Applications

Nicolas Loubet, Stephane Monfray, G. Bidal, 2010 .

Unbiased line width roughness measurements with critical dimension scanning electron microscopy and critical dimension atomic force microscopy

Olivier Joubert, Marc Fouchier, Erwine Pargon, 2012 .

Benefits of plasma treatments on critical dimension control and line width roughness transfer during gate patterning

Olivier Joubert, Marc Fouchier, Erwine Pargon, 2013 .

Si1-xGex/Si Selective Etch with HCl for Thin Si-Channel Transistors Integration

Nicolas Loubet, Stephane Denorme, Thomas Skotnicki, 2007 .