Anton Karputkin

Probabilistic equivalence checking based on high-level decision diagrams

Anton Karputkin, Raimund Ubar, Mati Tombak, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Synthesis of High-Level Decision Diagrams for functional test pattern generation

Anton Karputkin, Raimund Ubar, Mati Tombak, 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints

Hideo Fujiwara, Anton Karputkin, Raimund Ubar, 2012, J. Electron. Test..

Verification and Error Correction on High-Level Decision Diagrams

Anton Karputkin, 2013 .

Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams

Anton Karputkin, Raimund Ubar, Mati Tombak, 2011, 2011 IEEE International High Level Design Validation and Test Workshop.

A synthesis-agnostic behavioral fault model for high gate-level fault coverage

Anton Karputkin, Jaan Raik, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Automated correction of design errors by edge redirection on High-Level Decision Diagrams

Anton Karputkin, Raimund Ubar, Mati Tombak, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011

Anton Karputkin, Raimund Ubar, Mati Tombak, 2011, HLDVT.

Canonical representations of high-level decision diagrams

Anton Karputkin, Raimund Ubar, Mati Tombak, 2010 .