Jaan Raik

发表

Probabilistic equivalence checking based on high-level decision diagrams

Anton Karputkin, Raimund Ubar, Mati Tombak, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Hierarchical Identification of Untestable Faults in Sequential Circuits

Raimund Ubar, Jaan Raik, Anna Krivenko, 2007 .

FPGA based fault emulation of synchronous sequential circuits

Raimund Ubar, Jaan Raik, Peeter Ellervee, 2004, Proceedings Norchip Conference, 2004..

Experimental comparison of different diagnosis algorithms in the BIST environment

Raimund Ubar, Jaan Raik, Sergei Kostin, 2007 .

Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems

Raimund Ubar, Jaan Raik, Sergei Kostin, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits

Raimund Ubar, Jaan Raik, Sergei Devadze, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

A Security Verification Template to Assess Cache Architecture Vulnerabilities

Cezar Reinbrecht, Jaan Raik, Said Hamdioui, 2020, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2008, 2008 13th European Test Symposium.

Automated test bench generation for high-level synthesis flow ABELITE

Raimund Ubar, Jaan Raik, Samary Baranov, 2011, 2011 9th East-West Design & Test Symposium (EWDTS).

Implementation-Independent Functional Test Generation for MSC Microprocessors

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2019, 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC).

Layout to Logic Defect Analysis for Hierarchical Test Generation

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers

Jaan Raik, Thomas Hollstein, Gert Jervan, 2015, NOCS.

Mutation analysis with high-level decision diagrams

Raimund Ubar, Jaan Raik, Franco Fummi, 2010, 2010 11th Latin American Test Workshop.

Fault-Aware Performance Assessment Approach for Embedded Networks

Jaan Raik, Frank Dannemann, Jan Malburg, 2019, 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Energy-Efficient Multi-fragment Markov Model Guided Online Model-Based Testing for MPSoC

Leonidas Tsiopoulos, Jaan Raik, Sven Nõmm, 2019 .

High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis

Jaan Raik, Maksim Jenihhin, Anton Chepurov, 2011 .

Research in Digital Design and Test at Tallinn University of Technology

Raimund Ubar, Jaan Raik, Margus Kruus, 2008 .

New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams

Raimund Ubar, Jaan Raik, Artjom Jasnetski, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Comprehensive performance and robustness analysis of 2D turn models for network-on-chips

Jaan Raik, Thomas Hollstein, Siavoosh Payandeh Azad, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Extensible open-source framework for translating RTL VHDL IP cores to SystemC

Jaan Raik, Maksim Jenihhin, Syed Saif Abrar, 2013, 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Multiple stuck-at-fault detection theorem

Raimund Ubar, Jaan Raik, Sergei Kostin, 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Definition of the Diagnostic Model

Rolf Drechsler, Alexander Finder, Jaan Raik, 2011 .

MODULE LEVEL DEFECT SIMULATION IN DIGITAL CIRCUITS

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2001 .

Overview of Fault Tolerant Techniques in Underwater Sensor Networks pdf

Jaan Raik, Maarja Kruusmaa, Lauri Vihman, 2019, ArXiv.

Testing Strategies for Networks on Chip

Raimund Ubar, Jaan Raik, R. Ubar, 2003, Networks on Chip.

Hierarchical identification of NBTI-critical gates in nanoscale logic

Fabian Vargas, Raimund Ubar, Jaan Raik, 2014, 2014 15th Latin American Test Workshop - LATW.

High-Level Decision Diagrams based coverage metrics for verification and test

Raimund Ubar, Jaan Raik, Uljana Reinsalu, 2009, 2009 10th Latin American Test Workshop.

High-level test generation for processing elements in many-core systems

Raimund Ubar, Jaan Raik, Siavoosh Payandeh Azad, 2017, 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).

Mixed hierarchical-functional fault models for targeting sequential cores

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2008, J. Syst. Archit..

Back-tracing and event-driven techniques in high-level simulation with decision diagrams

Raimund Ubar, Jaan Raik, Adam Morawiec, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

BASTION: Board and SoC test instrumentation for ageing and no failure found

Jaan Raik, Hans G. Kerkhoff, Matteo Sonza Reorda, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Structurally synthesized multiple input BDDs for simulation of digital circuits

Raimund Ubar, Jaan Raik, Artur Jutman, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Parallel exact critical path tracing fault simulation with reduced memory requirements

Raimund Ubar, Jaan Raik, Sergei Devadze, 2009, 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era.

FoREnSiC- An Automatic Debugging Environment for C Programs

Rolf Drechsler, Alexander Finder, Görschwin Fey, 2012, Haifa Verification Conference.

Hardware Modeling for Design Verification and Debug

Jaan Raik, Maksim Jenihhin, Anton Tsepurov, 2013 .

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs

Raimund Ubar, Jaan Raik, Sergei Devadze, 2005, EDCC.

SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints

Jaan Raik, Peeter Ellervee, Thomas Hollstein, 2016, 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).

Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling

Rolf Drechsler, Robert Schmidt, Jaan Raik, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

Methods for Improving the Accuracy and Efficiency of Fault Simulation in Digital Systems. Meetodid digitaalsüsteemide rikete simuleerimise täpsuse ja efektiivsuse tõstmiseks

Jaan Raik, Raimund-Johannes Ubar, 2019 .

Scalable algorithm for structural fault collapsing in digital circuits

Raimund Ubar, Jaan Raik, Lembit Jurimagi, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Comprehensive Abstraction of VHDL RTL Cores to ESL SystemC. Register-siirde taseme VHDL kirjelduste kompleksne abstraheerimine süsteemitaseme SystemC mudeliteks

Jaan Raik, Maksim Jenihhin, 2016 .

Handling of SETs on NoC Links by Exploitation of Inherent Redundancy in Circular Input Buffers

Jaan Raik, Siavoosh Payandeh Azad, Gert Jervan, 2018, 2018 16th Biennial Baltic Electronics Conference (BEC).

Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips

Raimund Ubar, Jaan Raik, Vineeth Govind, 2009, IET Comput. Digit. Tech..

A scalable model based RTL framework zamiaCAD for static analysis

Jaan Raik, Maksim Jenihhin, Rainer Dorsch, 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

Requirements & Concept of the Diagnostic Model

Alexander Finder, Jaan Raik, Görschwin Fey, 2010 .

QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications

Jaan Raik, Massimo Violante, Siavoosh Payandeh Azad, 2018, 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

High-Level Test Synthesis with Hierarchical Test Generation

Petru Eles, Raimund Ubar, Jaan Raik, 1999 .

Fault Diagnosis in Integrated Circuits with BIST

Raimund Ubar, Jaan Raik, Sergei Kostin, 2007 .

Formal Verification and Error Correction on High-Level Decision Diagrams. Formaalne verifitseerimine ja vigade parandamine kõrgtasemelistel otsustusdiagrammidel

Mati Tombak, Jaan Raik, Raimund-Johannes Ubar, 2012 .

2012 JETTA Reviewers

Luigi Carro, Fernando Morgado Dias, Irith Pomeranz, 2013, J. Electron. Test..

High-level design error diagnosis using backtrace on decision diagrams

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2010, NORCHIP 2010.

Application Specific True Critical Paths Identification in Sequential Circuits

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Foreword

Jaan Raik, Krishnendu Chakrabarty, Thomas Hollstein, 2016, VLSI-SoC.

Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits

Hideo Fujiwara, Raimund Ubar, Jaan Raik, 2011, 2011 Sixteenth IEEE European Test Symposium.

Advanced technical education in the age of cyber physical systems

Heinrich Theodor Vierhaus, Raimund Ubar, Jaan Raik, 2014, 10th European Workshop on Microelectronics Education (EWME).

A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers

Jaan Raik, Siavoosh Payandeh Azad, Tara Ghasempouri, 2018, 2018 IEEE International Test Conference in Asia (ITC-Asia).

Synthesis of High-Level Decision Diagrams for functional test pattern generation

Anton Karputkin, Raimund Ubar, Mati Tombak, 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

Test Synthesis from Register-Transfer Level Descriptions

Jaan Raik, Priidu Paomets, 1996 .

Hierarchical Test Generation Based on Alternative Graph Models

Jaan Raik, J. Raik, 1999 .

Gate-level modelling of NBTI-induced delays under process variations

Fabian Vargas, Raimund Ubar, Jaan Raik, 2016, 2016 17th Latin-American Test Symposium (LATS).

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements

Jaan Raik, Zainalabedin Navabi, Maksim Jenihhin, 2019, 2019 IEEE East-West Design & Test Symposium (EWDTS).

Hardware Modeling for Design Verification and Debug. Riistvara modelleerimine disaini verifitseerimise ja silumise jaoks

Jaan Raik, Maksim Jenihhin, 2013 .

Design and Test Technology for Dependable Systems-on-Chip

Heinrich Theodor Vierhaus, Raimund Ubar, Jaan Raik, 2010 .

Multi-level fault simulation of digital systems on decision diagrams

Raimund Ubar, Jaan Raik, Eero Ivask, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

Software-Based Mitigation for Memory Address Decoder Aging

Jaan Raik, Said Hamdioui, Mottaqiallah Taouil, 2019, 2019 IEEE Latin American Test Symposium (LATS).

Engineering of an Effective Automatic Dynamic Assertion Mining Platform

Jaan Raik, Graziano Pravadelli, Jan Malburg, 2019, 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC).

Design Understanding: From Logic to Specification*

Görschwin Fey, Jaan Raik, Heinz Riener, 2018, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

DECIDER: A Decision Diagram Based Hierarchical Test Generation System

Raimund Ubar, Jaan Raik, Gert Jervan, 1998 .

Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2020, Microprocess. Microsystems.

Towards Formal Verification of Cache Access-based Side-Channel Attacks

Cezar Reinbrecht, Jaan Raik, Johanna Sepulveda, 2019 .

DECIDER: A SYSTEM FOR HIERARCHICAL TEST PATTERN GENERATION

Raimund Ubar, Jaan Raik, 2003 .

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2019, 2019 IEEE European Test Symposium (ETS).

Environment for FPGA-based Fault Emulation

Raimund Ubar, Jaan Raik, Peeter Ellervee, 2006 .

Sequential circuit test generation using decision diagram models

Raimund Ubar, Jaan Raik, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Untestable Fault Identification in Sequential Circuits Using Model-Checking

Hideo Fujiwara, Raimund Ubar, Jaan Raik, 2008, 2008 17th Asian Test Symposium.

PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2009, J. Electron. Test..

Hierarchical test generation for combinational circuits with real defects coverage

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2002, Microelectron. Reliab..

Automated Design Error Localization in RTL Designs

Raimund Ubar, Jaan Raik, Heinz-Dietrich Wuttke, 2014, IEEE Design & Test.

Multi-view modeling for MPSoC design aspects

Leonidas Tsiopoulos, Jaan Raik, Maksim Jenihhin, 2018, 2018 16th Biennial Baltic Electronics Conference (BEC).

Software-Level TMR Approach for On-Board Data Processing in Space Applications

Görschwin Fey, Jaan Raik, Thomas Hollstein, 2018, 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Functional TestGeneration forFinite State Machines

Raimund Ubar, Jaan Raik, Artur Jutman, 2006 .

Dependability Improvements of NoC-Based Systems. Töökindluse parandamine kiipvõrkudel põhinevates süsteemides

Jaan Raik, Gert Jervan, Gert Jervan, 2018 .

Web-Based Framework for Parallel Distributed Test

Raimund Ubar, Jaan Raik, Eero Ivask, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

FP7 collaborative research project DIAMOND: Diagnosis, error modeling and correction for reliable systems design

Jaan Raik, 2012, 2012 17th IEEE European Test Symposium (ETS).

AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links

Jaan Raik, Siavoosh Payandeh Azad, Gert Jervan, 2018, 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).

Parallel X-fault simulation with critical path tracing technique

Raimund Ubar, Jaan Raik, Sergei Devadze, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability

Ian O'Connor, Jaan Raik, Sergei Kostin, 2016, IFIP Advances in Information and Communication Technology.

Cycle-based simulation with decision diagrams

Raimund Ubar, Jaan Raik, Adam Morawiec, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Simulation-Based Hardware Verification with High-Level Decision Diagrams. Simuleerimisel põhinev riistvara verifitseerimine kõrgtaseme otsustusdiagrammidel

Raimund Ubar, Jaan Raik, R. Ubar, 2008 .

Ultra-low latency NoC testing via pseudo-random test pattern compaction

Jaan Raik, Alessandro Strano, Davide Bertozzi, 2012, 2012 International Symposium on System on Chip (SoC).

Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems

Raimund Ubar, Jaan Raik, Sergei Kostin, 2009, 2009 IEEE International Conference on Microelectronic Systems Education.

Timing-critical path analysis with structurally synthesized BDDs

Raimund Ubar, Jaan Raik, Vladimir Viies, 2018, 2018 7th Mediterranean Conference on Embedded Computing (MECO).

On efficient logic-level simulation of digital circuits represented by the SSBDD model

Raimund Ubar, Jaan Raik, Artur Jutman, 2002, 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595).

Understanding multidimensional verification: Where functional meets non-functional

Dan Alexandrescu, Jaan Raik, Tara Ghasempouri, 2019, Microprocess. Microsystems.

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits

Raimund Ubar, Jaan Raik, Sergei Kostin, 2018, 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Test Configurations for Diagnosing Faulty Links in NoC Switches

Raimund Ubar, Jaan Raik, Vineeth Govind, 2007, 12th IEEE European Test Symposium (ETS'07).

Designing Reliable Cyber-Physical Systems

Jaan Raik, Hans G. Kerkhoff, Sergei Devadze, 2018 .

About robustness of test patterns regarding multiple faults

Raimund Ubar, Jaan Raik, Sergei Kostin, 2012, 2012 13th Latin American Test Workshop (LATW).

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Jaan Raik, Thomas Hollstein, Gert Jervan, 2015, 2015 Euromicro Conference on Digital System Design.

Turbo Tester: A CAD System for Teaching Digital Test

Raimund Ubar, Jaan Raik, Gert Jervan, 1998 .

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints

Hideo Fujiwara, Anton Karputkin, Raimund Ubar, 2012, J. Electron. Test..

High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory

Raimund Ubar, Jaan Raik, Manfred Glesner, 2002 .

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Jaan Raik, Tara Ghasempouri, Maksim Jenihhin, 2018, 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

Cycle-based simulation algorithms for digital systems using high-level decision diagrams (poster paper)

Raimund Ubar, Jaan Raik, Adam Morawiec, 2000, DATE '00.

Automated design error debug using high-level decision diagrams and mutation operators

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2013, Microprocess. Microsystems.

Hierarchical Test Generation with Multi-Level Decision Diagram

Raimund Ubar, Jaan Raik, Gert Jervan, 1998 .

Dependability Improvements of NoC-Based Systems

Jaan Raik, Gert Jervan, Behrad Niazmand, 2018 .

Defect-oriented module-level fault diagnosis in digital circuits

Raimund Ubar, Jaan Raik, Sergei Kostin, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Sequential Test Set Compaction in LFSR Reseeding

Jaan Raik, Artur Jutman, Igor Aleksejev, 2011 .

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation

Giovanni Squillero, Raimund Ubar, Jaan Raik, 2014, EvoApplications.

Comparison of Model-Based Error Localization algorithms for C designs

Jaan Raik, Urmas Repinski, J. Raik, 2013, East-West Design & Test Symposium (EWDTS 2013).

Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing

Jaan Raik, Maksim Jenihhin, Ahmet Cagri Bagbaba, 2019, 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs

Raimund Ubar, Jaan Raik, Elmet Orasson, 2015, VLSI-SoC.

Code Coverage Analysis using High-Level Decision Diagrams

Raimund Ubar, Jaan Raik, Peeter Ellervee, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

Constraints Solving Based Hierarchical Test Generation for Synchronous Sequential Circuits. Kitsenduste lahendamisel baseeruv hierarhiline testigenereerimine sünkroonsetele järjestikskeemidele

Jaan Raik, 2012 .

Fault Emulation on FPGA: A Feasibility Study

Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, 2003 .

Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits

Raimund Ubar, Jaan Raik, Lembit Jurimagi, 2015, 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC).

Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations

Raimund Ubar, Jaan Raik, Peeter Ellervee, 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

On Test Generation for Microprocessors for Extended Class of Functional Faults

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2019, VLSI-SoC.

Targeting Conditional Operations in Sequential Test Pattern Generation

Raimund Ubar, Jaan Raik, 2004 .

Modeling Microprocessor Faults on High-Level Decision Diagrams

Raimund Ubar, Jaan Raik, Heinz-Dietrich Wuttke, 2008 .

Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis

Jaan Raik, Massimo Violante, Siavoosh Payandeh Azad, 2018, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

At-speed self-testing of high-performance pipe-lined processing architectures

Raimund Ubar, Jaan Raik, Sergei Devadze, 2013, 2013 NORCHIP.

PSL assertion checkers synthesis with ASM based HLS tool ABELITE

Jaan Raik, Samary Baranov, Maksim Jenihhin, 2012, 2012 13th Latin American Test Workshop (LATW).

New categories of Safe Faults in a processor-based Embedded System

Raimund Ubar, Jaan Raik, Matteo Sonza Reorda, 2019, 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Defect-oriented test- and layout-generation for standard-cell ASIC designs

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

A CAD SYSTEM FOR TEACHING DIGITAL TEST

Raimund Ubar, Jaan Raik, Eero Ivask, 1998 .

Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams

Anton Karputkin, Raimund Ubar, Mati Tombak, 2011, 2011 IEEE International High Level Design Validation and Test Workshop.

Structural fault collapsing by superposition of BDDs for test generation in digital circuits

Raimund Ubar, Jaan Raik, Artur Jutman, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Abstraction of clock interface for conversion of RTL VHDL to SystemC

Jaan Raik, Maksim Jenihhin, Syed Saif Abrar, 2014, 2014 IEEE International Advance Computing Conference (IACC).

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

Fabian Vargas, Giovanni Squillero, Raimund Ubar, 2016, J. Electron. Test..

Investigations of the diagnosibility of digital networks with BIST

Raimund Ubar, Jaan Raik, Sergei Kostin, 2009, 2009 10th Latin American Test Workshop.

A novel random approach to diagnostic test generation

Raimund Ubar, Jaan Raik, Sergei Kostin, 2016, 2016 IEEE Nordic Circuits and Systems Conference (NORCAS).

Diagnostic modelling of digital systems with multi-level decision diagrams

Raimund Ubar, Jaan Raik, Margus Kruus, 2006 .

Web-Based Environment for Digital Electronics Test Tools

Raimund Ubar, Jaan Raik, André Schneider, 2004, Virtual Enterprises and Collaborative Networks.

An approach for PSL assertion coverage analysis with high-level decision diagrams

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2010, 2010 East-West Design & Test Symposium (EWDTS).

PASCAL: Timing SCA Resistant Design and Verification Flow

Jaan Raik, Kolin Paul, Maksim Jenihhin, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Semiconductor Technology, Design and Test Roadmap

Raimund Ubar, Jaan Raik, 2003 .

Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2001, Microelectron. Reliab..

FSMD RTL design manipulation for clock interface abstraction

Jaan Raik, Maksim Jenihhin, Syed Saif Abrar, 2015, 2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits

Raimund Ubar, Jaan Raik, Sergei Devadze, 2010, 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications.

Internet-based collaborative test generation with MOSCITO

Raimund Ubar, Jaan Raik, André Schneider, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Logic-based implementation of fault-tolerant routing in 3D network-on-chips

Jaan Raik, Jose Flich, Thomas Hollstein, 2016, 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

Critical Path Tracing Based Simulation of Transition Delay Faults

Raimund Ubar, Jaan Raik, Sergei Devadze, 2014, 2014 17th Euromicro Conference on Digital System Design.

A synthesis-agnostic behavioral fault model for high gate-level fault coverage

Anton Karputkin, Jaan Raik, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

On the Reuse of TLM Mutation Analysis at RTL

Raimund Ubar, Jaan Raik, Franco Fummi, 2012, J. Electron. Test..

Embedded fault diagnosis in digital systems with BIST

Raimund Ubar, Jaan Raik, Sergei Kostin, 2008, Microprocess. Microsystems.

Evolutionary Approach to Test Generation for Functional BIST pdf

Raimund Ubar, Jaan Raik, D. E. Ivanov, 2010, ArXiv.

Combining dynamic slicing and mutation operators for ESL correction

Raimund Ubar, Jaan Raik, Franco Fummi, 2012, 2012 17th IEEE European Test Symposium (ETS).

Performance analysis of cosimulating processor core in VHDL and SystemC

Jaan Raik, Maksim Jenihhin, Syed Saif Abrar, 2013, 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

Cross-Layer Dependability Management in Network on Chip based System on Chip. Kiipvõrkudel põhinevate süsteemide kihtideülene usaldatavuse haldus

Jaan Raik, Thomas Hollstein, Gert Jervan, 2018 .

Status on Reasoning Engines and Dynamic Techniques

Rolf Drechsler, Alexander Finder, Jaan Raik, 2010 .

Modeling and simulation of circuits with shared structurally synthesized BDDs

Raimund Ubar, Jaan Raik, Vladimir Viies, 2017, Microprocess. Microsystems.

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs

Raimund Ubar, Jaan Raik, Sergei Devadze, 2007, 12th IEEE European Test Symposium (ETS'07).

How to Prove that a Circuit is Fault-Free?

Raimund Ubar, Jaan Raik, Sergei Kostin, 2012, 2012 15th Euromicro Conference on Digital System Design.

Teaching research in the laboratory using diagnosis environment for digital systems

Raimund Ubar, Jaan Raik, Sergei Kostin, 2009, 2009 EAEEIE Annual Conference.

Defect-oriented fault simulation and test generation in digital circuits

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

Designing reliable cyber-physical systems overview associated to the special session at FDL'16

Yong Zhao, Görschwin Fey, Jaan Raik, 2016, 2016 Forum on Specification and Design Languages (FDL).

Multi-Fragment Markov Model Guided Online Test Generation for MPSoC

Leonidas Tsiopoulos, Jaan Raik, Jüri Vain, 2017, ICTERI.

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2020, J. Electron. Test..

Fast identification of true critical paths in sequential circuits

Raimund Ubar, Jaan Raik, Sergei Kostin, 2018, Microelectron. Reliab..

Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra

Raimund Ubar, Jaan Raik, Sergei Devadze, 2015, Microprocess. Microsystems.

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG

Fabian Vargas, Giovanni Squillero, Jaan Raik, 2015, 2015 16th Latin-American Test Symposium (LATS).

Hierarchical Test Pattern Generation and Untestability Identification Techniques for Synchronous Sequential Circuits. Hierarhilised testigenereerimise ja mittetestitavuse identifitseerimise meetodid sünkroonsetele järjestikskeemidele

Jaan Raik, 2010 .

Efficient Fault Injection based on Dynamic HDL Slicing Technique

Jaan Raik, Maksim Jenihhin, Ahmet Cagri Bagbaba, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Efficient hierarchical approach to test generation for digital systems

Raimund Ubar, Jaan Raik, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

Automated minimization of concurrent online checkers for Network-on-Chips

Jaan Raik, Thomas Hollstein, Gert Jervan, 2015, 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).

Fault-resilient NoC router with transparent resource allocation

Jaan Raik, Siavoosh Payandeh Azad, Gert Jervan, 2017, 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).

Hierarchical physical defect reasoning in digital circuits

Raimund Ubar, Jaan Raik, Sergei Kostin, 2011 .

Defect-oriented mixed-level fault simulation in digital systems

Raimund Ubar, Jaan Raik, Eero Ivask, 2002 .

HIERARCHICAL TEST GENERATION FOR DIGITAL SYSTEMS

Raimund Ubar, Jaan Raik, Gert Jervan, 1998 .

SSBDDs and Double Topology for Multiple Fault Reasoning

Raimund Ubar, Jaan Raik, Sergei Kostin, 2013 .

Decision Diagram Based Test Methods for Digital Systems

Jaan Raik, 2008 .

A PC-BASED CAD SYSTEM FOR TRAINING DIGITAL TEST

Raimund Ubar, Jaan Raik, Ahto Buldas, 1994 .

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores

Jaan Raik, Maksim Jenihhin, Syed Saif Abrar, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Automated correction of design errors by edge redirection on High-Level Decision Diagrams

Anton Karputkin, Raimund Ubar, Mati Tombak, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Mutation-Based Verification and Error Correction in High-Level Designs. Mutatsioonidel põhinev verifitseerimine ja vigade parandamine kõrgtaseme skeemides

Jaan Raik, Jaanika Raik, 2015 .

DOT: new deterministic defect-oriented ATPG tool

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2005, European Test Symposium (ETS'05).

Parallel Critical Path Tracing Fault Simulation in Sequential Circuits

Raimund Ubar, Jaan Raik, Sergei Kostin, 2018, 2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES).

Functional self-test of high-performance pipe-lined signal processing architectures

Raimund Ubar, Jaan Raik, Sergei Devadze, 2015, Microprocess. Microsystems.

A Constraint-Driven Gate-Level Test Generator

Raimund Ubar, Jaan Raik, Helena Krupnova, 2005 .

From online fault detection to fault management in Network-on-Chips: A ground-up approach

Raimund Ubar, Jaan Raik, Thomas Hollstein, 2017, 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Fabian Vargas, Raimund Ubar, Jaan Raik, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations

Raimund Ubar, Jaan Raik, 2000, J. Electron. Test..

Mutation analysis for SystemC designs at TLM

Raimund Ubar, Jaan Raik, Franco Fummi, 2011, 2011 12th Latin American Test Workshop (LATW).

Dependability evaluation in fault-tolerant systems with high-level decision diagrams

Raimund Ubar, Jaan Raik, Peeter Ellervee, 2007 .

RT-level test point insertion for sequential circuits

Raimund Ubar, Jaan Raik, Vineeth Govind, 2004, First International Workshop onTestability Assessment, 2004. IWoTA 2004. Proceedings..

Macro level defect-oriented diagnosability of digital circuits

Raimund Ubar, Jaan Raik, Sergei Kostin, 2010, 2010 12th Biennial Baltic Electronics Conference.

Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs

Giovanni Squillero, Raimund Ubar, Jaan Raik, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

A New Testability Calculation Method to Guide RTL Test Generation

Raimund Ubar, Jaan Raik, Tanel Nõmmeots, 2005, J. Electron. Test..

Bonfire kiipvõrgu jõudlus analüüs. Performance analysis of Bonfire Network on Chip

Jaan Raik, Siavoosh Payandeh Azad, Behrad Niazmand, 2016 .

Assessment of diagnostic test for automated bug localization

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2013, 2013 14th Latin American Test Workshop - LATW.

Constraint-based test pattern generation at the Register-Transfer Level

Raimund Ubar, Jaan Raik, Anna Krivenko, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Hierarchical Identification of Untestable Faults in Sequential Circuits

Raimund Ubar, Jaan Raik, Anna Krivenko, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

From RTL Liveness Assertions to Cost-Effective Hardware Checkers

Jaan Raik, Tara Ghasempouri, Behrad Niazmand, 2018, 2018 Conference on Design of Circuits and Integrated Systems (DCIS).

Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance

Raimund Ubar, Jaan Raik, Sergei Devadze, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics

Jaan Raik, Siavoosh Payandeh Azad, Tara Ghasempouri, 2018, 2018 IEEE International Test Conference in Asia (ITC-Asia).

A Hybrid Fault Injection Methodology for Real Time Systems

Alfredo Benso, Paolo Prinetto, Raimund Ubar, 1998 .

Raimund Ubar, Jaan Raik, Uljana Reinsalu, 2010, 2010 12th Biennial Baltic Electronics Conference.

Immortalizing many-core systems early experiences of the horizon 2020 action IMMORTAL

Jaan Raik, 2015, 2015 International Conference on High Performance Computing & Simulation (HPCS).

A tool for random test generation targeting high diagnostic resolution

Raimund Ubar, Jaan Raik, Sergei Kostin, 2016, 2016 15th Biennial Baltic Electronics Conference (BEC).

Fast static compaction of tests composed of independent sequences: basic properties and comparison of methods

Raimund Ubar, Jaan Raik, Artur Jutman, 2002, 9th International Conference on Electronics, Circuits and Systems.

A scalable technique to identify true critical paths in sequential circuits

Raimund Ubar, Jaan Raik, Sergei Kostin, 2017, 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Improved fault emulation for synchronous sequential circuits

Raimund Ubar, Jaan Raik, Peeter Ellervee, 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

Evaluating Fault Emulation on FPGA

Jaan Raik, Peeter Ellervee, Kalle Tammemäe, 2004, FPL.

Identifying NBTI-Critical Paths in Nanoscale Logic

Fabian Vargas, Raimund Ubar, Jaan Raik, 2013, 2013 Euromicro Conference on Digital System Design.

Synthesis of multiple fault oriented test groups from single fault test sets

Raimund Ubar, Jaan Raik, Sergei Kostin, 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

DfT-based External Test and Diagnosis of Mesh-like Networks on Chips. Testitavusel põhinev välise testi ja diagnoosi meetod kahemõõtmelistele kiipvõrkudele

Jaan Raik, 2009 .

Combined fault-model free cause-effect and effect-cause fault diagnosis in block-level digital networks

Raimund Ubar, Jaan Raik, Sergei Kostin, 2009, 2009 1st Asia Symposium on Quality Electronic Design.

Cost-Effective Concurrent Hardware Checkers for Network on Chip based System on Chip. Kulutõhusad süsteemiga paralleelsed rikkemonitorid kiipvõrkudel põhinevatele kiipsüsteemidele

Jaan Raik, Tara Ghasempouri, 2019 .

Report on Reasoning Engines and Dynamic Techniques

Rolf Drechsler, Alexander Finder, Jaan Raik, 2011 .

Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2012, 2012 13th Latin American Test Workshop (LATW).

Fault Diagnosis in Integrated Circuits with BIST

Raimund Ubar, Jaan Raik, Sergei Kostin, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Logic simulation and fault collapsing with shared structurally synthesized bdds

Raimund Ubar, Jaan Raik, Dmitri Mironov, 2014, 2014 19th IEEE European Test Symposium (ETS).

Multiple-objective backtrace for solving test generation constraints

Jaan Raik, A. Mekler, 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).

Distributed Approach for Genetic Test Generation in the Field of Digital Electronics

Raimund Ubar, Jaan Raik, Eero Ivask, 2008, IDC.

Extended checkers for Logic-Based Distributed Routing in Network-on-Chips

Jaan Raik, Thomas Hollstein, Behrad Niazmand, 2014, 2014 14th Biennial Baltic Electronic Conference (BEC).

Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems pdf

Jaan Raik, Thomas Hollstein, Siavoosh Payandeh Azad, 2016, ArXiv.

Mixed-level defect simulation in data-paths of digital systems

Raimund Ubar, Jaan Raik, Eero Ivask, 2002, 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595).

FPGA based fault emulation of synchronous sequential circuits

Raimund Ubar, Jaan Raik, Peeter Ellervee, 2004 .

2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011

Anton Karputkin, Raimund Ubar, Mati Tombak, 2011, HLDVT.

Double Phase Fault Collapsing with Linear Complexity in Digital Circuits

Raimund Ubar, Jaan Raik, Artur Jutman, 2010, 2015 Euromicro Conference on Digital System Design.

Jõudluse ja energiatarbe hindamine mittelenduval mälul põhineval mälusisesel arvutusel ja mäluhierarhialPerformance and Energy Evaluation of NVM-Based CIM and Memory Hierarchy

Jaan Raik, Kolin Paul, 2019 .

Comparison of Genetic and Random Techniques for Test Pattern Generation

Raimund Ubar, Jaan Raik, Eero Ivask, 1998 .

Localization of Bugs in Processor Designs Using zamiaCAD Framework

Jaan Raik, Heinz-Dietrich Wuttke, Maksim Jenihhin, 2012, 2012 13th International Workshop on Microprocessor Test and Verification (MTV).

Hierarchical Test Generation Based

Jaan Raik, J. Raik, 1997 .

Fault Simulation and Code Coverage Analysis of RTL Designs Using High-Level Decision Diagrams. Rikete simuleerimine ja koodikatte analüüs register-siirde tasemel kasutades kõrgtaseme otsustusdiagramme

Jaan Raik, Peeter Ellervee, Aleksander Sudnitsõn, 2013 .

High-Level Decision Diagram based Fault Models for Targeting FSMs

Raimund Ubar, Jaan Raik, Taavi Viilukas, 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems

Dan Alexandrescu, Heinrich Theodor Vierhaus, Zoya Dyka, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Application of high-level decision diagrams for simulation-based verification tasks

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2010 .

Parallel fault backtracing for calculation of fault coverage

Raimund Ubar, Jaan Raik, Sergei Devadze, 2008, 2008 Asia and South Pacific Design Automation Conference.

Digital logic simulation with compressed BDDs

Raimund Ubar, Jaan Raik, Sergei Devadze, 2011, 2011 IEEE International Conference on Computer Science and Automation Engineering.

Automated area and coverage optimization of minimal latency checkers

Jaan Raik, Thomas Hollstein, Siavoosh Payandeh Azad, 2017, 2017 22nd IEEE European Test Symposium (ETS).

Reseeding using compaction of pre-generated LFSR sub-sequences

Raimund Ubar, Jaan Raik, Artur Jutman, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Exploiting high-level descriptions for circuits fault tolerance assessments

Alfredo Benso, Paolo Prinetto, Raimund Ubar, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

An educational environment for digital testing: hardware, tools, and Web-based runtime platform

Raimund Ubar, Jaan Raik, Artur Jutman, 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

RTL Assertion Mining with Automated RTL-to-TLM Abstraction

Jaan Raik, Graziano Pravadelli, Nicola Bombieri, 2019, 2019 Forum for Specification and Design Languages (FDL).

Mixed-level identification of fault redundancy in microprocessors

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2019, 2019 IEEE Latin American Test Symposium (LATS).

CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector

Jaan Raik, Peeter Ellervee, Tara Ghasempouri, 2021, 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Triple Fixed-Point MAC Unit for Deep Learning

Jaan Raik, Kalle Tammemäe, Thomas Hollstein, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules

Raimund Ubar, Jaan Raik, Maksim Jenihhin, 2021, 2021 24th Euromicro Conference on Digital System Design (DSD).

Verifying cache architecture vulnerabilities using a formal security verification flow

Cezar Reinbrecht, Jaan Raik, Said Hamdioui, 2021 .

A Methodology for Automated Mining of Compact and Accurate Assertion Sets

Jaan Raik, Tara Ghasempouri, Gert Jervan, 2021, 2021 IEEE Nordic Circuits and Systems Conference (NorCAS).

Side-Channel Attacks on Triple Modular Redundancy Schemes

Levent Aksoy, Jaan Raik, Felipe Almeida, 2021, 2021 IEEE 30th Asian Test Symposium (ATS).

Design Space Exploration of SABER in 65nm ASIC

Jaan Raik, Sujoy Sinha Roy, Felipe Almeida, 2021, IACR Cryptol. ePrint Arch..