Ramy E. Aly

Dual sense amplified bit lines (DSABL) architecture for low-power SRAM design

Mohamed A. Elgamel, Magdy A. Bayoumi, Ramy E. Aly, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Low-Power Cache Design Using 7T SRAM Cell

Magdy A. Bayoumi, Ramy E. Aly, M. Bayoumi, 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Family of 32 nm IA Processors

Ramy E. Aly, Christopher Mozak, Nasser A. Kurd, 2011, IEEE Journal of Solid-State Circuits.

Novel 7T sram cell for low power cache design

Magdy A. Bayoumi, Ramy E. Aly, Md. Ibrahim Faisal, 2005, Proceedings 2005 IEEE International SOC Conference.

Precharged SRAM cell for ultra low-power on-chip cache

Magdy A. Bayoumi, Ramy E. Aly, 2005, Proceedings 2005 IEEE International SOC Conference.

High-Speed and Low-Power IP for Embedded Block Coding with Optimized Truncation (EBCOT) Sub-Block in JPEG2000 System Implementation

Magdy A. Bayoumi, Ramy E. Aly, 2006, J. VLSI Signal Process..