R. Loo

发表

60Gb/s waveguide-coupled O-band GeSi quantum-confined Stark effect electro-absorption modulator

Joris Van Campenhout, Yoojin Ban, S. Balakrishnan, 2021, 2021 Optical Fiber Communications Conference and Exhibition (OFC).

Lateral and vertical scaling of a QSA HBT for a 0.13/spl mu/m 200GHz SiGe:C BiCMOS technology

S. Decoutere, L. Witters, N. Ouassif, 2004, Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting.

A Novel Deep Trench Isolation Featuring Airgaps for a High-Speed 0.13μm SiGe:C BiCMOS Technology

S. Decoutere, S. Van Huylenbroeck, P. Leray, 2006, 2006 International Symposium on VLSI Technology, Systems, and Applications.

High-mobility Si1−xGex-channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths

C. Ortolland, L. Witters, H. Bender, 2010, 2010 Symposium on VLSI Technology.

Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

L. Witters, N. Waldron, N. Collaert, 2013, 2013 IEEE International Electron Devices Meeting.

Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.

R. Rooyackers, G. Eneman, S. Biesemans, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Challenges and Opportunities for Vertical Nanowire FETs: Device Design and Fabrication

J. Ryckaert, D. Mocuta, G. Eneman, 2018, Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials.

High-mobility 0.85nm-EOT Si0.45Ge0.55-pFETs: Delivering high performance at scaled VDD

A. Mercha, L. Witters, J. Mitard, 2010, 2010 International Electron Devices Meeting.

Performance and electrostatic improvement by high-pressure anneal on Si-passivated strained Ge pFinFET and gate all around devices with superior NBTI reliability

L. Witters, D. Mocuta, N. Collaert, 2017, 2017 Symposium on VLSI Technology.

25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions

R. Rooyackers, N. Collaert, G. Eneman, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

R. Rooyackers, E. Augendre, N. Collaert, 2006, 2006 International Electron Devices Meeting.

Influence of the Ge-concentration and RTA on the device performance of strained Si/SiGe pMOS devices

N. Collaert, P. Verheyen, M. Caymax, 2002, 32nd European Solid-State Device Research Conference.

8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

L. Witters, H. Bender, T. Chiarella, 2010, 2010 Symposium on VLSI Technology.

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

A Novel Fully Self-Aligned SiGe:C HBT Architecture Featuring a Single-Step Epitaxial Collector-Base Process

G.A.M. Hurkx, S. Decoutere, T. Vanhoucke, 2007, 2007 IEEE International Electron Devices Meeting.

15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

A. Brand, P. Eyben, L. Witters, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Selective epitaxial deposition of strained silicon: a simple and effective method for fabricating high performance MOSFET devices

Wilfried Vandervorst, K. De Meyer, Romain Delhougne, 2004 .

Processing aspects in the low-frequency noise of nMOSFETs on strained-silicon substrates

E. Simoen, C. Claeys, G. Eneman, 2006, IEEE Transactions on Electron Devices.

High-performance strained Si/SiGe pMOS devices with multiple quantum wells

Nadine Collaert, K. De Meyer, Matty Caymax, 2002 .

1mA/um-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D

P. Eyben, G. Hellings, L. Witters, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

Gang Wang, Wilfried Vandervorst, Marc Heyns, 2010 .

Selectively grown vertical Si-p MOS transistor with short channel lengths

T. Grabolla, Hans Lüth, Lili Vescan, 1996 .

Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs

Rita Rooyackers, Anne Vandooren, Guido Groeseneken, 2013 .

Use of high order precursors for manufacturing gate all around devices

Naoto Horiguchi, Liesbeth Witters, Andriy Hikavyy, 2017 .

Impact of Epi-Si growth temperature on Ge-pFET performance

B. Kaczer, G. Hellings, J. Mitard, 2009, 2009 Proceedings of the European Solid State Device Research Conference.

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

L. Witters, N. Waldron, D. Mocuta, 2017, IEEE Transactions on Electron Devices.

Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

R. Rooyackers, N. Collaert, S. Biesemans, 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

Tensely strained silicon on SiGe produced by strain transfer

Reinhard Carius, Matty Caymax, Dan Buca, 2004 .

A 50 nm vertical Si/sub 0.70/Ge/sub 0.30//Si/sub 0.85/Ge/sub 0.15/ pMOSFET with an oxide/nitride gate dielectric

M. Van Rossum, N. Collaert, K. De Meyer, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

Vertical ordering of islands in Ge-Si multilayers

Wolfgang Jäger, H. Trinkaus, R. Loo, 1996 .

On the beneficial impact of tensile-strained silicon substrates on the low-frequency noise of n-channel metal-oxide-semiconductor transistors

Eddy Simoen, C. Claeys, K. De Meyer, 2005 .

A model of threading dislocation density in strain-relaxed Ge and GaAs epitaxial films on Si (100)

Gang Wang, Eddy Simoen, Marc Heyns, 2009 .

Ge nFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipole formation

L. Witters, N. Collaert, S. Sioncke, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Improved thermal stability of Ni-silicides on Si: C epitaxial layers

Matty Caymax, Matthias Bauer, Peter Verheyen, 2007 .

Processing Technologies for Advanced Ge Devices

Naoto Horiguchi, Jerome Mitard, Liesbeth Witters, 2017 .

Optimization of the MuGFET performance on Super Critical-Strained SOI (SC-SSOI) substrates featuring raised source/drain and dual CESL

B. Ghyselen, R. Rooyackers, E. Augendre, 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

High Quality Ge Virtual Substrates on Si Wafers with Standard STI Patterning

Guy Brammertz, Matty Caymax, Shotaro Takeuchi, 2010 .

On the Low-Frequency Noise of pMOSFETs With Embedded SiGe Source/Drain and Fully Silicided Metal Gate

E. Simoen, C. Claeys, P. Verheyen, 2007, IEEE Electron Device Letters.

Low-frequency noise assessment of the silicon passivation of Ge pMOSFETs

Jerome Mitard, E. Simoen, C. Claeys, 2010 .

Strain Enhanced nMOS Using In Situ Doped Embedded $\hbox{Si}_{1 - x}\hbox{C}_{x}$ S/D Stressors With up to 1.5% Substitutional Carbon Content Grown Using a Novel Deposition Process

H. Bender, S. Biesemans, D. Shamiryan, 2008, IEEE Electron Device Letters.

Integration challenges for multi-gate devices

R. Rooyackers, S. De Gendt, S. Locorotondo, 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

Challenges and opportunities in advanced Ge pMOSFETs

Geert Hellings, Jerome Mitard, Eddy Simoen, 2012 .

Reliable 50Gb/s silicon photonics platform for next-generation data center optical interconnects

J. De Coster, S. Balakrishnan, K. Croes, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Molecular beam deposition of Al2O3 on p-Ge(001)/Ge0.95Sn0.05 heterostructure and impact of a Ge-cap interfacial layer

Wilfried Vandervorst, Yosuke Shimura, Matty Caymax, 2011 .

(Invited) Electrical Characterization of Ge-pFETs with HfO2/TiN Metal Gate: Review of Possible Defects Impacting the Hole Mobility

Jerome Mitard, Marc Heyns, Marc Meuris, 2010 .

Characterization of GeSn materials for future Ge pMOSFETs source/drain stressors

Yosuke Shimura, Matty Caymax, Shigeaki Zaima, 2011 .

Valence band energy in confined Si1−xGex (0.28

Andre Stesmans, Marc Meuris, Laurent Souriau, 2009 .

Challenges for introducing Ge and III/V devices into CMOS technologies

B. Kaczer, G. Hellings, L. Witters, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Layout Scaling of $\hbox{Si}_{1-x}\hbox{Ge}_{x} \hbox{-Channel}$ pFETs

C. Ortolland, L. Witters, J. Mitard, 2011, IEEE Transactions on Electron Devices.