Meng-Fan Chang

发表

A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization

Xin Si, Shouyi Yin, Shaojun Wei, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Session 16 Overview: Computation in Memory Memory Subcommittee

Seung-Jun Bae, Meng-Fan Chang, Ru Huang, 2021, ISSCC.

Sparsity-Aware Clamping Readout Scheme for High Parallelism and Low Power Nonvolatile Computing-in-Memory Based on Resistive Memory

Chunmeng Dou, Ming Liu, Linfang Wang, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control

Qi Liu, Xin Si, Yongpan Liu, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating

Nan Sun, Huazhong Yang, Yongpan Liu, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A 6.54-to-26.03 TOPS/W Computing-In-Memory RNN Processor using Input Similarity Optimization and Attention-based Context-breaking with Output Speculation

Shouyi Yin, Ruiqi Guo, Zhixiao Zhang, 2021, 2021 Symposium on VLSI Circuits.

A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning

Xin Si, Jingjing Li, Qiang Li, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source

Xiaoyu Sun, Shimeng Yu, Bin Gao, 2021, IEEE Journal of Solid-State Circuits.

A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation

Arijit Raychowdhury, Yu-Der Chih, Win-San Khwa, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, IEEE Journal of Solid-State Circuits.

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

Xin Si, Shyh-Shyuan Sheu, Ting-Wei Chang, 2022, IEEE Journal of Solid-State Circuits.

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

CiM3D: Comparator-in-Memory Designs Using Monolithic 3-D Technology for Accelerating Data-Intensive Applications

Jia-Min Shieh, Jack Sampson, Cheng-Xin Xue, 2021, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference

Boris Murmann, Yu-Der Chih, Subhasish Mitra, 2021, 2021 Symposium on VLSI Circuits.

Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices

Cheng-Xin Xue, Je-Min Hung, Chuan-Jia Jhang, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection

Arijit Raychowdhury, Yu-Der Chih, Win-San Khwa, 2022, IEEE Journal of Solid-State Circuits.

29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification

Arijit Raychowdhury, Yu-Der Chih, Win-San Khwa, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device

Yen-Cheng Chiu, Yu-Der Chih, Cheng-Xin Xue, 2021, IEEE Journal of Solid-State Circuits.

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

Hidehiro Fujiwara, Tan-Li Chou, Yu-Der Chih, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel

Tzu-Hsiang Hsu, Chung-Chuan Lo, Ren-Shuo Liu, 2021, IEEE Journal of Solid-State Circuits.

Ultra-Low Power 3D NC-FinFET-based Monolithic 3D+ -IC with Computing-in-Memory for Intelligent IoT Devices

Guo-Wei Huang, Jia-Min Shieh, Chih-Chao Yang, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

TSV-free FinFET-based Monolithic 3D+-IC with computing-in-memory SRAM cell for intelligent IoT devices

Guo-Wei Huang, Jia-Min Shieh, Chih-Chao Yang, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

A 210mV 7.3MHz 8T SRAM with dual data-aware write-assists and negative read wordline for high cell-stability, speed and area-efficiency

Hiroyuki Yamauchi, Lai-Fu Chen, Meng-Fan Chang, 2013, 2013 Symposium on VLSI Circuits.

Three-Dimensional $\hbox{4F}^{2}$ ReRAM With Vertical BJT Driver by CMOS Logic Compatible Process

Heng-Yuan Lee, Ming-Jinn Tsai, Ya-Chin King, 2011, IEEE Transactions on Electron Devices.

A 210mV 7.3MHz 8T SRAM with dual data-aware write-assists and negative read wordline for high cell-stability, speed and area-efficiency

Hiroyuki Yamauchi, Lai-Fu Chen, Meng-Fan Chang, 2013, 2013 Symposium on VLSI Technology.