Natsuyuki Koda

FPGA-based transceiver circuit for labeling signal transmission system

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2017, 2017 International SoC Design Conference (ISOCC).

36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector

Hiroshi Inoue, Akira Tsuchiya, Kosuke Furuichi, 2016, 2016 International SoC Design Conference (ISOCC).

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS

Hideyuki Nosaka, Shinsuke Nakano, Masafumi Nogawa, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

FPGA-Based Binary Labeling Signal Transmission System

Akira Tsuchiya, Ryosuke Noguchi, Keiji Kishine, 2019 .

10-Gb/s Data Frame Generation Circuit with Frequency Modulation in 65-nm CMOS

Kosuke Furuichi, Hiromu Uemura, Keiji Kishine, 2018 .

Design of High-linearity Delay Detection Circuit for 10-Gb/s Communication System in 65-nm CMOS

Kosuke Furuichi, Hiromu Uemura, Keiji Kishine, 2017 .

Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system

Kosuke Furuichi, Hiromu Uemura, Keiji Kishine, 2016, 2016 International SoC Design Conference (ISOCC).

Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS

Kosuke Furuichi, Hiromu Uemura, Keiji Kishine, 2016, 2016 International SoC Design Conference (ISOCC).

Simple and Low Power Highly Sensitive Frequency Demodulator Circuit for 10-Gb/s Transmission System for Labeling Signal

Hiromu Uemura, Keiji Kishine, Hiromi Inaba, 2017 .