Ting-Kuei Kuan

A Loop Gain Optimization Technique for Integer-$N$ TDC-Based Phase-Locked Loops

Shen-Iuan Liu, Ting-Kuei Kuan, Ting-Kuei Kuan, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 0.43pJ/bit true random number generator

Shen-Iuan Liu, Ting-Kuei Kuan, Yu-Hsuan Chiang, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS

Mark Chen, Chih-Hsien Chang, Ting-Kuei Kuan, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS

Chih-Hsien Chang, Ting-Kuei Kuan, Ruei-Pin Shen, 2019, 2019 Symposium on VLSI Circuits.

A digital MDLL using switched biasing technique to reduce low-frequency phase noise

Shen-Iuan Liu, Ting-Kuei Kuan, Chang-Cheng Huang, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 7-nm FinFET CMOS PLL With 388-fs Jitter and −80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control

Ting-Kuei Kuan, Ruei-Pin Shen, Chen-Ting Ko, 2020, IEEE Journal of Solid-State Circuits.

A Subharmonically Injection-Locked All-Digital PLL Without Main Divider

Shen-Iuan Liu, Ting-Kuei Kuan, Kai-Hui Zeng, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques

Shen-Iuan Liu, Ting-Kuei Kuan, Ting-Kuei Kuan, 2016, IEEE Journal of Solid-State Circuits.

A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction

Shen-Iuan Liu, Ting-Kuei Kuan, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth

Shen-Iuan Liu, Ting-Kuei Kuan, Chih-Lu Wei, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.