S. Pateras

Design of a self-reconfiguring interconnection network for fault-tolerant VLSI processor arrays

J. Rajski, S. Pateras, 1989 .

BIST: a test a diagnosis methodology for complex, high reliability electronics systems

S. Pateras, P. McHugh, 1997, 1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century.

Built-In Self-Test (BIST) in the era of deep sub-micron technology

S. Pateras, B. Koenemann, B. Koenemann, 1996, IEEE Technical Applications Conference. Northcon/96. Conference Record.

Will Test Compression Run Out Of Gas

S. Pateras, 2008 .

Security vs. test quality: fully embedded test approaches are the key to having both

S. Pateras, 2004 .

Self-reconfiguring interconnection network for a fault-tolerant mesh-connected array of processors

J. Rajski, S. Pateras, 1988 .

Testing systems on a chip

R. Chandramouli, S. Pateras, R. Chandramouli, 1996 .

Influence de la dispersion d’oxydes et d’une phase intermétallique sur le comportement mécanique d’alliages ferritiques élaborés par mécanosynthèse

C. Prioul, S. Pateras, A. Alamo, 1993 .

A self-reconfiguration scheme for fault-tolerant VLSI processor arrays

Janusz Rajski, S. Pateras, 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

A comparison of structural test approaches

S. Pateras, 2004, IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No.04CH37585).

Cost trade-offs of various design for test techniques

S. Pateras, H.B. Druckerman, M.P. Kusko, 1994, Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing.