H. Kato

3.3 volt sense-amplifier schemes suitable for 4 Mb BiCMOS SRAMs

A. Suzuki, H. Kato, T. Kobayashi, 1992, Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting.

SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober

H. Kato, M. Matsui, K. Ochii, 1997 .

A 9 ns 4 Mb BiCMOS SRAM with 3.3 V operation

H. Kato, T. Kobayashi, K. Ochii, 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A Novel Synchronous Timing Control For 200mhz Mega-bits BiCMOS SRAM at 2.5V Operation

H. Kato, A. Suzuki, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

Consideration Of Poly-SI Loaded Cell Capacity Limits For Each Of Low-power And High-speed SRAM's

H. Kato, K. Ochii, K. Hashimoto, 1991, 1991 Symposium on VLSI Circuits.