Masaya Miyahara

发表

Designing of a 10MHz BW 77dB SNDR 8.1mW Continuous-Time Delta-Sigma Modulator With a Proposed Low Power, Rail-to-Rail Output Swing OPAMP

Akira Matsuzawa, Hong Phuc Ninh, Masaya Miyahara, 2010 .

A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation

Kenichi Okada, Ahmed Musa, Akira Matsuzawa, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers

Akira Matsuzawa, Masaya Miyahara, Lilan Yu, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency

Akira Matsuzawa, Masaya Miyahara, Tohru Kaneko, 2015, IEICE Trans. Electron..

A 83-dB SFDR 10-MHz bandwidth continuous-time Delta-Sigma modulator employing a one-element-shifting dynamic element matching

Akira Matsuzawa, Hong Phuc Ninh, Masaya Miyahara, 2011 .

A digitally-calibrated 20-Gb/s 60-GHz direct-conversion transceiver in 65-nm CMOS

Kenichi Okada, Ning Li, Ahmed Musa, 2013, 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS

Akira Matsuzawa, Masaya Miyahara, Abdel Martinez Alonso, 2018, IEEE Journal of Solid-State Circuits.

A 10b 320 MS/s 40 mW open-loop interpolated pipeline ADC

Akira Matsuzawa, Masaya Miyahara, Hyunui Lee, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance

Kenichi Okada, Ning Li, Hanli Liu, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 0.8 ps-LSB, 10-bit, 0.018 mm 2 Time-to-Digital Converter

Akira Matsuzawa, Zule Xu, 松澤昭, 2014 .

A 7GS/s Complete-DDFS-Solution in 65nm CMOS

Akira Matsuzawa, Masaya Miyahara, Abdel Martinez Alonso, 2018, IEICE Trans. Electron..

A 12-bit interpolated pipeline ADC using body voltage controlled amplifier

Akira Matsuzawa, Masaya Miyahara, Hyunui Lee, 2013, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS).

A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 bit Flash ADC

Akira Matsuzawa, James Lin, Masaya Miyahara, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers

Akira Matsuzawa, Masaya Miyahara, Lilan Yu, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Study of Low Power Wideband VGA with Current Amplifiers

Matsuzawa Akira, Masaya Miyahara, Hirose Koji, 2016 .

A 6-bit subranging ADC with single CDAC interpolation

Akira Matsuzawa, Masaya Miyahara, Hyunui Lee, 2013, 2013 IEEE International Conference of Electron Devices and Solid-state Circuits.

A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier

Akira Matsuzawa, Zule Xu, James Lin, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture

Akira Matsuzawa, Masaya Miyahara, Abdel Martinez Alonso, 2016, IEICE Trans. Electron..

A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing

Akira Matsuzawa, Masaya Miyahara, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS

Akira Matsuzawa, Masaya Miyahara, Abdel Martinez Alonso, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input

Akira Matsuzawa, Masaya Miyahara, Tohru Kaneko, 2017, IEICE Trans. Electron..

Connectivity in Wireless Telecommunications

Mizuki Motoyoshi, Minoru Fujishima, Masaomi Tsuru, 2019 .

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC

Kenichi Okada, Akira Matsuzawa, Zule Xu, 2016, IEEE Journal of Solid-State Circuits.

A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC

Akira Matsuzawa, Zhijie Chen, Masaya Miyahara, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

A 0.022mm2 970µW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuits

Kenichi Okada, Ahmed Musa, Akira Matsuzawa, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

Kenichi Okada, Ahmed Musa, Akira Matsuzawa, 2014, IEEE Journal of Solid-State Circuits.

A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers

Akira Matsuzawa, Masaya Miyahara, Lilan Yu, 2016, IEEE Journal of Solid-State Circuits.

C-12-22 Study of High Speed Encoder Using in Flash A/D Converter

Kenichi Okada, Akira Matsuzawa, Masaya Miyahara, 2007 .

A 83-dB SFDR 10-MHz bandwidth continuous-time Delta-Sigma modulator employing a one-element-shifting dynamic element matching

Akira Matsuzawa, Hong Phuc Ninh, Masaya Miyahara, 2011, 2011 IEEE International Symposium on Radio-Frequency Integration Technology.

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology

Akira Matsuzawa, Yu Hou, Masaya Miyahara, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry

Kenichi Okada, Ning Li, Ahmed Musa, 2013, IEEE Journal of Solid-State Circuits.

High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator

Akira Matsuzawa, Zule Xu, Masaya Miyahara, 2017, IEICE Trans. Electron..

Proposal of layout-driven 1/2.8 size DAC design methodology

Akira Matsuzawa, Kenji Mori, 松澤昭, 2013 .

A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC

Akira Matsuzawa, Zule Xu, Masaya Miyahara, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter

Akira Matsuzawa, Masaya Miyahara, Koji Hirose, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator

Akira Matsuzawa, Masaya Miyahara, Jeonghoon Han, 2014, IEICE Trans. Electron..

An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques

Akira Matsuzawa, Masaya Miyahara, Daehwa Paik, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

25.2 A 2.2GHz −242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture

Kenichi Okada, Akira Matsuzawa, Satoshi Kondo, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

Akira Matsuzawa, James Lin, Seungjong Lee, 2015, IEEE Journal of Solid-State Circuits.

A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology

Akira Matsuzawa, Zhijie Chen, Yu Hou, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture

Akira Matsuzawa, Masaya Miyahara, Abdel Martinez Alonso, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier

Akira Matsuzawa, Masaya Miyahara, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

Radio receiver front-end using time-based all-digital ADC (TAD)

Akira Matsuzawa, Masanobu Suzuki, Yuji Kamiya, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A 2.2 GHz -242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture

Kenichi Okada, Akira Matsuzawa, Satoshi Kondo, 2016, IEEE Journal of Solid-State Circuits.

A 6bit, 7mW, 250fJ, 700MS/s subranging ADC

Akira Matsuzawa, Masaya Miyahara, Kei Yoshihara, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique

Akira Matsuzawa, James Lin, Masaya Miyahara, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A High-Speed Clock-Scalable Dynamic Amplifier for Mixed-Signal Applications

Akira Matsuzawa, Masaya Miyahara, James Lin, 2011 .

A 2nd order fully-passive noise-shaping SAR ADC with embedded passive gain

Akira Matsuzawa, Zhijie Chen, Masaya Miyahara, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Highly Linear Open-Loop Amplifiers Using Nonlinearity Cancellation and Gain Adapting Techniques

Akira Matsuzawa, Masaya Miyahara, Lilan Yu, 2016, IEICE Trans. Electron..

A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS

Akira Matsuzawa, Masaya Miyahara, Abdel Martinez Alonso, 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay

Kenichi Okada, Ning Li, Ahmed Musa, 2017, IEEE Journal of Solid-State Circuits.

A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC

Akira Matsuzawa, Masaya Miyahara, Zhijie Chen, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier

Akira Matsuzawa, Masaya Miyahara, 2018, IEICE Electron. Express.

A time-domain architecture and design method of high speed A-to-D converters with standard cells

Akira Matsuzawa, Shiro Dosho, Masaya Miyahara, 2011, IEEE Asian Solid-State Circuits Conference 2011.

A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise

Akira Matsuzawa, Zule Xu, Masaya Miyahara, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time

Akira Matsuzawa, Masaya Miyahara, 2007, IEICE Trans. Electron..

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance

Kenichi Okada, Ning Li, Satoshi Kondo, 2019, IEEE Journal of Solid-State Circuits.

A 2 GHz 3.1 mW type-I digital ring-based PLL

Kenichi Okada, Akira Matsuzawa, Zule Xu, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS

Akira Matsuzawa, Zule Xu, Masaya Miyahara, 2013, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS).

A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier

Kenichi Okada, Akira Matsuzawa, Masaya Miyahara, 2018, 2018 IEEE Symposium on VLSI Circuits.

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC

Akira Matsuzawa, Zule Xu, Seungjong Lee, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

All-digital 0.016mm2 reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS

Akira Matsuzawa, Yu Hou, Masaya Miyahara, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Fully Passive Noise Shaping Techniques in a Charge-Redistribution SAR ADC

Akira Matsuzawa, Zhijie Chen, Masaya Miyahara, 2016, IEICE Trans. Electron..

A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation

Akira Matsuzawa, Masaya Miyahara, Hyunui Lee, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Special Section on Analog Circuits and Related SoC Integration Technologies Design of Interpolated Pipeline ADC using Low-Gain Open-Loop Amplifiers

Akira Matsuzawa, Masaya Miyahara, Hyunui Lee, 2013 .

A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells

Akira Matsuzawa, Masaya Miyahara, Tohru Kaneko, 2018, IEICE Trans. Electron..

Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product

Akira Matsuzawa, James Lin, Masaya Miyahara, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers

Kenichi Okada, Akira Matsuzawa, Masaya Miyahara, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Design of CMOS Low-Noise Analog Circuits for Particle Detector Pixel Readout LSIs

Fei Li, Akira Matsuzawa, Masaya Miyahara, 2013, IEICE Trans. Electron..

A 7-bit 1-GS/s Flash ADC with Background Calibration

Sanroku Tsukamoto, Akira Matsuzawa, Masaya Miyahara, 2014, IEICE Trans. Electron..

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry

Kenichi Okada, Ning Li, Ahmed Musa, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers

Akira Matsuzawa, James Lin, Seungjong Lee, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique

Akira Matsuzawa, James Lin, Masaya Miyahara, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

A 2 GS/s 118 mW digital-mapping direct digital frequency synthesizer in 65nm CMOS

Akira Matsuzawa, Xia Yuan, Masaya Miyahara, 2017, 2017 12th European Microwave Integrated Circuits Conference (EuMIC).

A study on the multi-bit-pipelined A/D converter

Akira Matsuzawa, Masaya Miyahara, Hiroki Endou, 2006 .

A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC

Akira Matsuzawa, Zule Xu, Seungjong Lee, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector

Akira Matsuzawa, Zule Xu, Kenichi Okada, 2019, IEICE Trans. Electron..

Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell

Kenichi Okada, Akira Matsuzawa, Zule Xu, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

19.5 An HCI-healing 60GHz CMOS transceiver

Kenichi Okada, Ahmed Musa, Akira Matsuzawa, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder

Akira Matsuzawa, Zhijie Chen, Masaya Miyahara, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof

Akira Matsuzawa, Toru Taniguchi, Yasuhiro Toriyama, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay

Kenichi Okada, Akira Matsuzawa, Satoshi Kondo, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

An analysis on a pseudo-differential dynamic comparator with load capacitance calibration

Akira Matsuzawa, Masaya Miyahara, Daehwa Paik, 2011, 2011 9th IEEE International Conference on ASIC.

An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator

Akira Matsuzawa, Masaya Miyahara, Daehwa Paik, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding

Kenichi Okada, Ahmed Musa, Akira Matsuzawa, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation

Kenichi Okada, Ahmed Musa, Akira Matsuzawa, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network

Kenichi Okada, Ning Li, Ahmed Musa, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs

Fei Li, Akira Matsuzawa, Masaya Miyahara, 2013, IEICE Trans. Electron..

A time-domain architecture and design method of high speed A-to-D converters with standard cells

Akira Matsuzawa, Shiro Dosho, Masaya Miyahara, 2011, IEEE Asian Solid-State Circuits Conference 2011.

An 84 dB dynamic range 62.5–625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier

Akira Matsuzawa, Masaya Miyahara, A. Matsuzawa, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

Kenichi Okada, Hans Herdian, Masaya Miyahara, 2021, IEEE Journal of Solid-State Circuits.

A low-offset latched comparator using zero-static power dynamic offset cancellation technique

Akira Matsuzawa, Masaya Miyahara, A. Matsuzawa, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

5 An HCI-Healing 60 GHz CMOS Transceiver

Kenichi Okada, Akira Matsuzawa, Satoshi Kondo, 2014 .

Picosecond Resolution Time-to-Digital Converter Using ${{\rm G}_{\rm m}} \hbox{-C}$ Integrator and SAR-ADC

Akira Matsuzawa, Zule Xu, Masaya Miyahara, 2014, IEEE Transactions on Nuclear Science.

A 10-bit, 290 fJ/conv. Steps, 0.13mm 2 , Zero-Static Power, Self-Timed Capacitance to Digital Converter

Akira Matsuzawa, T. Kurashina, Masaya Miyahara, 2009 .

A 10-bit , 290 fJ / conv . steps , 0 . 13 mm 2 , Zero-Static Power Self-Clocking Capacitance to Digital Converter

Akira Matsuzawa, Takashi Kurashina, Masaya Miyahara, 2009 .

A 12b 50/70 MS/s 2.2/4.6 mW 0.03mm 2 CMOS SAR ADC for a frequency, performance, and power scalable ADC

Akira Matsuzawa, Masaya Miyahara, Seungjong Lee, 2013 .

A Varactor-Less and Dither-Less LC-Digitally Controlled Oscillator with 9-bit Fine Bank, 0.26 mm 2 Area, and 6.7 kHz Frequency Resolution

Akira Matsuzawa, Zule Xu, Mitsutoshi Sugawara, 2014 .

3 A 64-QAM 60 GHz CMOS Transceiver with 4-Channel Bonding

Kenichi Okada, Akira Matsuzawa, Satoshi Kondo, 2013 .

Qpix v.1: A high speed 400-pixels readout LSI with 10-bit 10MSps pixel ADCs

Akira Matsuzawa, Masaya Miyahara, Fei Li, 2010 .

Picosecond Resolution Time-to-Digital Converter Using G mC Integrator and SAR-ADC

Akira Matsuzawa, Zule Xu, Masaya Miyahara, 2022 .

An Op-amp free SAR-VCO hybrid ADC with second-order noise shaping

Akira Matsuzawa, Masaya Miyahara, Yu Hou, 2016, 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Qpix v.1: A high speed 400-pixels readout LSI with 10-bit 10 MSps pixel ADCs

Fei Li, Akira Matsuzawa, Masaya Miyahara, 2011 .

A new particle detector LSI, Qpix: Integrating high speed ADC for each pixel

Fei Li, Akira Matsuzawa, T. Kurashina, 2010 .