Zhiyi Yu

发表

A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains

Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 167-Processor Computational Platform in 65 nm CMOS

Zhiyi Yu, D.N. Truong, W.H. Cheng, 2009, IEEE Journal of Solid-State Circuits.

Task-binding based branch-and-bound algorithm for NoC mapping

Zhiyi Yu, Liyang Zhou, Ming-e Jing, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A Shared Memory Module for Asynchronous Arrays of Processors

Zhiyi Yu, Michael J. Meeuwsen, Bevan M. Baas, 2007, EURASIP J. Embed. Syst..

EVALUATION OF NETWORK ON CHIP

Zhiyi Yu, Xiaoyang Zeng, Xichao Ma, 2014 .

Research on the heat transfer and flow characteristics of fin-tube exchanger under low pressure environment

Zhiyi Yu, Jin Guo, Run-ze Jia, 2017 .

Low-Cost Adaptive Exponential Integrate-and-Fire Neuron Using Stochastic Computing

Wei Liu, Zhiyi Yu, Shanlin Xiao, 2020, IEEE Transactions on Biomedical Circuits and Systems.

A fully programmable frame synchronization architecture of OFDM systems implemented on a multi-core processor platform

Zhiyi Yu, Xiaoyang Zeng, Yun Chen, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

A reconfigurable and deadlock-free routing algorithm for 2D Mesh Network-on-Chip

Zhiyi Yu, Xiaoyang Zeng, Zewen Shi, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

A low-cost architecture for multi-mode Reed-Solomon decoder

Wei Meng, Yun Chen, Zhiyi Yu, 2012, 2012 International SoC Design Conference (ISOCC).

High performance and energy efficient multi-core systems for DSP applications

Zhiyi Yu, Zhiyi Yu, 2007 .

Performance and power analysis of globally asynchronous locally synchronous multiprocessor systems

Zhiyi Yu, Bevan M. Baas, Zhiyi Yu, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

A secondary synchronization signal detection implementation for LTE downlink on a multi-core processor platform

Zhiyi Yu, Xiaoyang Zeng, Xueqiu Yu, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection

Zhiyi Yu, Yuhao Guo, Wenkang Liao, 2020, ISCAS.

H.264 video parallel decoder on a 24-core processor

Zhiyi Yu, Zheng Yu, Xiaoyang Zeng, 2013, 2013 IEEE 10th International Conference on ASIC.

A method of quadratic programming for mapping on NoC architecture

Jiayi Sheng, Zhiyi Yu, Ming-e Jing, 2011, 2011 9th IEEE International Conference on ASIC.

Numerical study of pressure fluctuation in the whole flow passage of a low specific speed mixed-flow pump

Zhiyi Yu, Baoshan Zhu, Wenwu Zhang, 2017 .

A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer

Hao Yu, Jie Lin, Zhiyi Yu, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors

Zhiyi Yu, Bevan M. Baas, Zhiyi Yu, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design

Zhiyi Yu, Xiaoyang Zeng, Jianwei Yang, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Efficient distributed memory management in a multi-core H.264 decoder on FPGA

Axel Jantsch, Zhonghai Lu, Jiajie Zhang, 2013, 2013 International Symposium on System on Chip (SoC).

A fast multi-core virtual platform and its application on software development

Zhiyi Yu, Dexue Zhang, Xiaoyang Zeng, 2013, 2013 IEEE 10th International Conference on ASIC.

An Efficient and Low-Overhead Chip-to-Chip Interconnect Protocol Design for NOC

Yi Luo, Cheng Li, Zhiyi Yu, 2019, 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA).

A 32×32B 65NM 4R/2W register file for low-power operation

Jun Han, Zhiyi Yu, Xiaoyang Zeng, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost

Zhiyi Yu, Yan Ying, Liyang Zhou, 2012, 2012 IEEE International Symposium on Circuits and Systems.

DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing

Zhiyi Yu, Zhang Zhang, Xin Cheng, 2020, IEICE Electron. Express.

BioSNet: A Fast-Learning and High-Robustness Unsupervised Biomimetic Spiking Neural Network pdf

Zhiyi Yu, Shanlin Xiao, Xingyu Yang, 2020, ArXiv.

Towards High-Performance and Energy-Efficient Multi-core Processors

Zhiyi Yu, Zhiyi Yu, 2010 .

A low power register file with asynchronously controlled read-isolation and software-directed write-discarding

Jiajie Zhang, Zhiyi Yu, Zheng Yu, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Detached-eddy simulation for time-dependent turbulent cavitating flows

Zhiyi Yu, Biao Huang, Guoyu Wang, 2012 .

NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators

Yi Luo, Cheng Li, Zhiyi Yu, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Many-Core Processors Granularity Evaluation by Considering Performance, Yield, and Lifetime Reliability

Wei Zhou, Zhiyi Yu, Xiaodong Zhang, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms

Zhiyi Yu, Yan Ying, Ming-e Jing, 2012, 2012 IEEE International Solid-State Circuits Conference.

Fast-Learning and High-Robustness Unsupervised Spiking Neural Networks with a Highly Parallel Inception-like Architecture

Zhiyi Yu, Shanlin Xiao, Xingyu Yang, 2019 .

Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks

Zhiyi Yu, Shanlin Xiao, Xingyu Yang, 2020, 2020 International Joint Conference on Neural Networks (IJCNN).

Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS

Zhiyi Yu, Zhang Zhang, Yibo Fan, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

AsAP: A Fine-Grained Many-Core Platform for DSP Applications

Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, 2007, IEEE Micro.

A Low-Cost and High-Throughput Virtual-Channel Router with Arbitration Optimization

Zhiyi Yu, Jian Wang, Yuhao Guo, 2019, 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA).

Efficient implementation of 3780-point FFT on a 16-core processor

Zhiyi Yu, Ming-e Jing, Xiaoyang Zeng, 2013, 2013 IEEE 10th International Conference on ASIC.

A low-area interconnect architecture for chip multiprocessors

Zhiyi Yu, Bevan M. Baas, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A control scheme for a 65nm 32×32b 4-read 2-write register file

Zhiyi Yu, Xiaoyang Zeng, Xingxing Zhang, 2011, 2011 9th IEEE International Conference on ASIC.

Mapping of pipeline flow chart onto mesh-based multi-core NoC architecture

Liang Liu, Zhiyi Yu, Dian Zhou, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Special Issue on Emerging Many-Core Systems for Exascale Computing

Hannu Tenhunen, Masoud Daneshtalab, Zhiyi Yu, 2015, ACM J. Emerg. Technol. Comput. Syst..

Functional verification methodology of a 32-bit RISC microprocessor

Bo Shen, Zhiyi Yu, Zhenyu Gu, 2002, IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions.

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process

Yi Li, Xu Cheng, Zhiyi Yu, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs pdf

Zhiyi Yu, Shanlin Xiao, Mingyuan Meng, 2020, 2020 25th International Conference on Pattern Recognition (ICPR).

A Flexible and Energy-Efficient Convolutional Neural Network Acceleration With Dedicated ISA and Accelerator

Zhiyi Yu, Xiaobai Chen, Zhiyi Yu, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform

Zhiyi Yu, Xiaoyang Zeng, Yun Chen, 2012, IEICE Trans. Inf. Syst..

A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue

Yun Chen, Zhiyi Yu, Yan Ying, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A novel network on chip architecture - Stargon

Zhiyi Yu, Xiaoyang Zeng, Xingxing Zhang, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform

Zhiyi Yu, Shuai Wang, Wei Huang, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

The write deduplication mechanism based on a novel low-power data latched sense amplifier for a magnetic tunnel junction based non-volatile memory

Zhiyi Yu, Ningyuan Yin, Baofa Huang, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

A channel estimator for LTE downlink mapped on a multi-core processor platform

Jiajie Zhang, Zhiyi Yu, Xiaoyang Zeng, 2011, 2011 9th IEEE International Conference on ASIC.

Evaluation of buffer organizations for network-on-chip

Zhiyi Yu, Weichao Zhou, Xiaoyang Zeng, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

Pipeline-based scheduling for heterogeneous multi-core systems

Derong Liu, Zhiyi Yu, Dian Zhou, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS

Zhiyi Yu, Xiaoyang Zeng, Jun Han, 2012, IEICE Electron. Express.

An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture

Jiayi Sheng, Zhiyi Yu, Dian Zhou, 2011, 2011 9th IEEE International Conference on ASIC.

An MTJ-Based Asynchronous System With Extremely Fine-Grained Voltage Scaling

Zhiyi Yu, Jianjun Chen, Xiaobai Chen, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals

Yi Ren, Zhiyi Yu, Xiaoyang Zeng, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Time-Division-Multiplexer based routing algorithm for NoC system

Zhiyi Yu, Liyang Zhou, Ming-e Jing, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A 65 nm Cryptographic Processor for High Speed Pairing Computation

Yang Li, Zhiyi Yu, Xiaoyang Zeng, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A global-aware bandwidth-constraint routing scheme for Network-on-Chip

Zhiyi Yu, Liulin Zhong, Xiaoyang Zeng, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A novel multi-core processor for communication applications

Zhiyi Yu, Xiaoyang Zeng, Bei Huang, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Integrated pipelined task scheduling and core mapping for streaming applications on multi-core systems

Zhiyi Yu, Xiaoyang Zeng, Mingze Ma, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Accurate Determination Of The Spin-Orbit Splitting Of The Valence Bands Of Silicon By Means Of Fourier Transform Photothermal Ionization Spectroscopy (FT-PTIS)

Zhiyi Yu, S. C. Shen, Y. X. Huang, 1989, Other Conferences.

Non-binary digital calibration for split-capacitor DAC in SAR ADC

Xu Cheng, Zhiyi Yu, Yawei Guo, 2015, IEICE Electron. Express.

A PUFs-based hardware authentication BLAKE algorithm in 65 nm CMOS

Zhiyi Yu, Xuelong Zhang, Yuejun Zhang, 2016 .

A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks

Jie Lin, Wei Zhou, Zhiyi Yu, 2013, 2013 IEEE 10th International Conference on ASIC.

A 2D mesh NoC with self-configurable and shared-FIFOs routers

Jie Lin, Wei Zhou, Zhiyi Yu, 2013, 2013 IEEE 10th International Conference on ASIC.

Performance of a 3-stage regenerative desalination system based on humidification-dehumidification process

Zhiyi Yu, Peng Cheng, Huifang Kang, 2015 .

Design of a high information-density multiple valued 2-read 1-write register file

Zhiyi Yu, Yuejun Zhang, Pengjun Wang, 2012, IEICE Electron. Express.

HYDRAULIC DESIGN OF A MULTIPHASE ROTODYNAMIC PUMP IMPELLER AND TEST VERIFICATION

Zhiyi Yu, 2006 .

An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture

Zhiyi Yu, Xiaoyang Zeng, Jun Han, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A configurable SoC design for information security

Yi Ren, Zhiyi Yu, Xiaoyang Zeng, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors

Zhiyi Yu, Bevan M. Baas, Zhiyi Yu, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Automatic Task Partition Method for Multi-core System

Zhiyi Yu, Yibo Fan, Ming-e Jing, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

A low power 1.0 GHz VCO in 65nm-CMOS LP-process

Xu Cheng, Zhiyi Yu, Zhang Zhang, 2011, 2011 9th IEEE International Conference on ASIC.

Implementation and optimization of 3780-point FFT on multi-core system

Jiayi Sheng, Zhiyi Yu, Ming-e Jing, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A fast and energy efficient FPGA-based system for real-time object tracking

Zhiyi Yu, Xiaobai Chen, Jinlong Xu, 2017, 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC).

Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles

Zhiyi Yu, Bevan M. Baas, 2006, 2006 International Conference on Computer Design.

A 130-nm ferroelectric nonvolatile system-on-chip for internet of things

Zhiyi Yu, 2019 .

Study of the Gas Distribution in a Multiphase Rotodynamic Pump Based on Interphase Force Analysis

Zhiyi Yu, Wenwu Zhang, Muhammad Zahid, 2018 .

An efficient parallel method for canopy clusteing with multi-core platform

Zhiyi Yu, Xiaoyang Zeng, Xichao Ma, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A multi-core-based heterogeneous parallel turbo decoder

Zhiyi Yu, Zhang Zhang, Xin Cheng, 2017, IEICE Electron. Express.

Design of a single-ended cell based 65nm 32×32b 4R2W register file

Zhiyi Yu, Xiaoyang Zeng, Xingxing Zhang, 2011, 2011 9th IEEE International Conference on ASIC.

A scalable and fault-tolerant routing algorithm for NoCs

Zhiyi Yu, Yan Ying, Xiaoyang Zeng, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array

Yi Li, Jie Lin, Jiajie Zhang, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation

Zhiyi Yu, Shuai Wang, Xiaoyang Zeng, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

Acceleration of MapReduce Framework on a Multicore Processor

Zhiyi Yu, Lijun Zhou, 2017 .

Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design

Zhiyi Yu, Xiaoyang Zeng, Jianwei Yang, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

A novel vector/SIMD multiply-accumulate unit based on reconfigurable booth array

Zhiyi Yu, Xiaoyang Zeng, Kaidi You, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

H.264 decoder on a 16-core processor with shared-memory and massage-passing communications

Zhiyi Yu, Zheng Yu, Jiajie Zhang, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs

Zhiyi Yu, Xiaoyang Zeng, Zewen Shi, 2011, 2011 9th IEEE International Conference on ASIC.

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing

Yi Li, Xu Cheng, Zhiyi Yu, 2014, IEICE Electron. Express.

Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform

Zhiyi Yu, Chen Chen, Xiaoyang Zeng, 2012, IEICE Trans. Commun..

A 16-Core Processor With Shared-Memory and Message-Passing Communications

Xu Cheng, Jiajie Zhang, Zhiyi Yu, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Evaluating performance of manycore processors with various granularities considering yield and lifetime reliability

Zhiyi Yu, Liulin Zhong, Xiaoyang Zeng, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs

Zhiyi Yu, Xiaoyang Zeng, Zewen Shi, 2011, IEICE Trans. Inf. Syst..

A Reconfigurable Process Engine for Flexible Convolutional Neural Network Acceleration

Zhiyi Yu, Shanlin Xiao, Xiaobai Chen, 2018, 2018 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC).

A fast multi-core virtual platform for performance evaluation of Network on Chip

Zhiyi Yu, Xiaoyang Zeng, Xichao Ma, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform

Qing Zhang, Zhiyi Yu, Xiaoyang Zeng, 2013, 2013 IEEE 10th International Conference on ASIC.

A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator

Chongshen Song, Hao Yu, Jie Lin, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

Architecture and Evaluation of an Asynchronous Array of Simple Processors

Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, 2008, J. Signal Process. Syst..

An FPGA-Based Hardware Accelerator for Traffic Sign Detection

Zhiyi Yu, Xin Li, Gary Overett, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fault tolerant computing for stream DSP applications using GALS multi-core processors

Zhiyi Yu, Xiaoyang Zeng, Zewen Shi, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Acceleration of Naive-Bayes algorithm on multicore processor for massive text classification

Jie Lin, Zhiyi Yu, Lijun Zhou, 2014, 2014 International Symposium on Integrated Circuits (ISIC).

High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning

Zhiyi Yu, Shanlin Xiao, Lei Bi, 2019, Neurocomputing.

Optical measurement system for characterizing compound semiconductor interface and surface states

Zhiyi Yu, Diana Convey, Jonathan K. Abrokwah, 1998, IEEE Trans. Instrum. Meas..

Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process

Zhiyi Yu, Zheng Yu, Xiaoyang Zeng, 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method

Zhiyi Yu, Shanlin Xiao, Zhiyu Li, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs

Zhiyi Yu, Shanlin Xiao, Mingyuan Meng, 2021, 2020 25th International Conference on Pattern Recognition (ICPR).

3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA

Zhiyi Yu, Shanlin Xiao, Huipeng Deng, 2021, 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Balancing the Cost and Performance Trade-Offs in SNN Processors

Zhiyi Yu, Shanlin Xiao, Xingyu Yang, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Simple High-Efficient Inter-Core Communication Mechanism for Multi-Core Systems

Zhiyi Yu, Xiaoyang Zeng, Kaidi You, 2011 .