G. Jaberipur

Posibits, negabits, and their mixed use in efficient realization of arithmetic algorithms

B. Parhami, G. Jaberipur, 2010, 2010 15th CSI International Symposium on Computer Architecture and Digital Systems.

Improved modulo-(2n ± 3) multipliers

G. Jaberipur, H. Ahmadifar, G. Jaberipur, 2013, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013).

A modulo 2n+1 multiplier with double-LSB encoding of residues

G. Jaberipur, H. Alavi, 2010, 2010 15th CSI International Symposium on Computer Architecture and Digital Systems.

Radix-10 addition with radix-1000 encoding of decimal operands

G. Jaberipur, S. Emami, M. Dorrigiv, 2012, The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012).

Weighted bit-set encodings for redundant digit sets: theory and applications

B. Parhami, G. Jaberipur, M. Ghodsi, 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..

A class of stored-transfer representations for redundant number systems

B. Parhami, G. Jaberipur, M. Ghodsi, 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).