Masaki Tsukude

发表

Highly reliable testing of ULSI memories with on-chip voltage-down converters

Hideto Hidaka, Masaki Tsukude, Kazutami Arimoto, 1993, IEEE Design & Test of Computers.

SOI-DRAM circuit technologies for low power high speed multigiga scale memories

Masaki Tsukude, Shigehiro Kuge, Fukashi Morishita, 1996 .

A new array architecture for parallel testing in VLSI memories

Masaki Tsukude, Kazutami Arimoto, Kazuyasu Fujishima, 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's

Masaki Tsukude, Takahiro Tsuruda, Michihiro Yamada, 1997 .

A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register

Masaki Tsukude, Kazuyasu Fujishima, Michihiro Yamada, 1989 .

Circuit design techniques for low-voltage operating and/or giga-scale DRAMs

Masaki Tsukude, Shigeki Tomishima, Tadato Yamagata, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

An experimental 256-Mb DRAM with boosted sense-ground scheme

Hideto Hidaka, Masaki Tsukude, Kazuyasu Fujishima, 1994 .

Column selection circuit in a semiconductor memory device

Hideto Hidaka, Masaki Tsukude, Kazutami Arimoto, 1992 .

Memory for random access with shared memory field

Hideto Hidaka, Masaki Tsukude, Kazutami Arimoto, 1992 .

FA 14.3: Circuit Design Techniques for Low-Voltage Operating andlor Giga-Scale DRAMS

Masaki Tsukude, Shigeki Tomishima, Tadato Yamagata, 1995 .

A speed-enhanced DRAM array architecture with embedded ECC

Masaki Tsukude, Kazuyasu Fujishima, K. Arimoto, 1990 .

A Blanket Source Line Architecture with Triple Metal for Giga Scale Memory LSIs (Special Issue on ULSI Memory Technology)

Masaki Tsukude, Shigehiro Kuge, Kazutami Arimoto, 1996 .

SOI-DRAM circuit technologies for low power high speed multi-giga scale memories

Masaki Tsukude, Shigehiro Kuge, Takahiro Tsuruda, 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

A Line-Mode Test with Data Register for ULSI Memory Architecture (Special Issue on LSI Memories)

Masaki Tsukude, Kazuyasu Fujishima, Tsukasa Ooishi, 1993 .

Semiconductor memory device with an on-chip contained test circuit and test methods for these

Masaki Tsukude, Kazutami Arimoto, Kazuyasu Fujishima, 1990 .

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme

Masaki Tsukude, Takeshi Fujino, Shigehiro Kuge, 1997, IEEE J. Solid State Circuits.

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs

Masaki Tsukude, Takahiro Tsuruda, Shigeki Tomishima, 1995 .

A 34 ns 256 Mb DRAM with boosted sense-ground scheme

Hideto Hidaka, Masaki Tsukude, Kazuyasu Fujishima, 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

A 60 ns 3.3 V 16 Mb DRAM

Masaki Tsukude, Kazuyasu Fujishima, Kazutami Arimoto, 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

A 34-ns 16-Mb DRAM with controllable voltage down-converter

Hideto Hidaka, Masaki Tsukude, Kazuyasu Fujishima, 1992 .

A Testing Technique for ULSI Memory with On-chip Voltage Down Converter

Hideto Hidaka, Masaki Tsukude, Kazutami Arimoto, 1992, Proceedings International Test Conference 1992.

with Boosted Sense-Ground Scheme

Hideto Hidaka, Masaki Tsukude, Kazutami Arimoto, 1993 .

A Smart Design Methodology with Distributed Extra Gate-Arrays for Advanced ULSI Memories (Special Issue on LSI Memories)

Hideto Hidaka, Masaki Tsukude, Kazutami Arimoto, 1993 .