Janardhan H. Satyanarayana

A hierarchical approach to transistor-level power estimation of arithmetic units

Keshab K. Parhi, Janardhan H. Satyanarayana, 1996, 1996 IEEE International Conference on Acoustics, Speech, and Signal Processing Conference Proceedings.

A New Technique for the High-Level Synthesis of Digit-Serial Digital Filters Based on Genetic Algorithms

Behrouz Nowrouzian, Janardhan H. Satyanarayana, 1997, J. Circuits Syst. Comput..

Theoretical analysis of word-level switching activity in the presence of glitching and correlation

Keshab K. Parhi, Janardhan H. Satyanarayana, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers

Keshab K. Parhi, Yun-Nan Chang, Leilei Song, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

Power Estimation of Digital Data Paths Using HEAT

Keshab K. Parhi, Janardhan H. Satyanarayana, 2000, IEEE Des. Test Comput..

Design and FPGA Implementation of Digit-Serial Modified Booth Multipliers

Behrouz Nowrouzian, Janardhan H. Satyanarayana, 1996, J. Circuits Syst. Comput..

Theoretical analysis of word-level switching activity in the presence of glitching and correlation

Keshab K. Parhi, Janardhan H. Satyanarayana, 2000, IEEE Trans. Very Large Scale Integr. Syst..

HEAT: hierarchical energy analysis tool

Keshab K. Parhi, Janardhan H. Satyanarayana, 1996, DAC '96.

Design and implementation of low-power digit-serial multipliers

Keshab K. Parhi, Yun-Nan Chang, Janardhan H. Satyanarayana, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.