Kundan Nepal

发表

Using Implications for Online Error Detection

R. Iris Bahar, Jennifer Dworak, Kundan Nepal, 2008, 2008 IEEE International Test Conference.

Design evolution of the trinity college IGVC robot ALVIN

David J. Ahlgren, Matthew Gillette, Kundan Nepal, 2004 .

Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing

Joel Grodstein, R. Iris Bahar, Kundan Nepal, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multi-floor Mapping and Navigation with Uncertainty

Kundan Nepal, James Ellingson, Megan Rose McGill, 2013 .

Compacting test vector sets via strategic use of implications

R. Iris Bahar, Jennifer Dworak, Kundan Nepal, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Dilated Temporal Convolutional Neural Network Architecture with Independent Component Layer for Human Activity Recognition

Hassan Salamy, Kundan Nepal, Matthew Ward, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Built-in Self-Repair in a 3D die stack using programmable logic

Xi Shen, Theodore W. Manikas, R. Iris Bahar, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Combinational hardware Trojan detection using logic implications

Kundan Nepal, Noah Cornell, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Wow! linear systems and signal processing is fun!

Maurice F. Aburdene, Kundan Nepal, 2011, 2011 Frontiers in Education Conference (FIE).

AC 2011-657: SATELLITE COMMUNICATIONS, DATA COMMUNICA- TIONS, AND SIMULATION

Maurice F. Aburdene, Kundan Nepal, Maurice Felix, 2011 .

Repairing a 3-D Die-Stack Using Available Programmable Logic

Theodore W. Manikas, R. Iris Bahar, Jennifer Dworak, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Satellite Communications, Data Communications, and Simulation

Maurice F. Aburdene, Kundan Nepal, 2011 .

CMOL cell assignment using exact shape of connectivity domain

Kundan Nepal, Joseph Norton, Chong Xu, 2015, 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO).

Design evolution of the Trinity College IGVC robot ALVIN

David J. Ahlgren, Matthew Gillette, Kundan Nepal, 2004, J. Field Robotics.

Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults

Carson Dunbar, Kundan Nepal, Kundan Nepal, 2011, J. Comput..

Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors

Kundan Nepal, 2012, 10th IEEE International NEWCAS Conference.

Designing logic circuits for probabilistic computation in the presence of noise

Joseph L. Mundy, R. Iris Bahar, William R. Patterson, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits

Joseph L. Mundy, R. Iris Bahar, William R. Patterson, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Apnea detection and respiration rate estimation through parametric modelling

Taikang Ning, Kundan Nepal, E. Biegeleisen, 2002, Proceedings of the IEEE 28th Annual Northeast Bioengineering Conference (IEEE Cat. No.02CH37342).

Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI Applications

Hassan Salamy, Kundan Nepal, Cheol-Hong Min, 2020, 2020 10th Annual Computing and Communication Workshop and Conference (CCWC).

Development of a Fundamentals of Electrical and Computing Systems Course for In-service K-12 Teachers

Kundan Nepal, Andrew Tubesing, 2014 .

Improving the testability and reliability of sequential circuits with invariant logic

R. Iris Bahar, Jennifer Dworak, Kundan Nepal, 2010, GLSVLSI '10.

Designing MRF based Error Correcting Circuits for Memory Elements

Joseph L. Mundy, R. Iris Bahar, William R. Patterson, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Optimizing noise-immune nanoscale circuits using principles of Markov random fields

Joseph L. Mundy, R. Iris Bahar, William R. Patterson, 2006, GLSVLSI '06.

Low-cost instrumentation of high-tunnels for a small co-op farm

Kundan Nepal, Jeremy Ziemer, Austin Stokes, 2019, 2019 IEEE Global Humanitarian Technology Conference (GHTC).

Test Architecture for Fine Grained Capture Power Reduction

Hui Jiang, Yi Sun, Jennifer Dworak, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Stimulating curiosity and the ability to formulate technical questions in an electric circuits course using the question formulation technique (QFT)

Kundan Nepal, Heath LeBlanc, Heath J. LeBlanc, 2017, 2017 IEEE Frontiers in Education Conference (FIE).

Tools for the 3Cs of Entrepreneurially Minded Learning (EML)

Kundan Nepal, Alan Cheville, Heath LeBlanc, 2018, 2018 IEEE Frontiers in Education Conference (FIE).

Designing Nanoscale Logic Circuits Based on Markov Random Fields

Joseph L. Mundy, R. Iris Bahar, William R. Patterson, 2007, J. Electron. Test..

MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits

Joseph L. Mundy, R. Iris Bahar, William R. Patterson, 2006, IEEE Micro.

Low cost Brussels sprouts harvester for small farms

Kundan Nepal, Milad Audi, Janssen Hang, 2019, 2019 IEEE Global Humanitarian Technology Conference (GHTC).

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack

Theodore W. Manikas, Yi Sun, R. Iris Bahar, 2019, J. Electron. Test..

A Cost Effective Approach for Online Error Detection Using Invariant Relationships

R. Iris Bahar, Jennifer Dworak, Kundan Nepal, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

RESTA: a robust and extendable symbolic timing analysis tool

Joel Grodstein, R. Iris Bahar, Kundan Nepal, 2004, GLSVLSI '04.

Timing analysis for full-custom circuits using symbolic DC formulations

Joel Grodstein, R. Iris Bahar, Kundan Nepal, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Using Existing Reconfigurable Logic in 3D Die Stacks for Test

Yi Sun, Xi Shen, Ping Gui, 2016, 2016 IEEE 25th North Atlantic Test Workshop (NATW).

Detecting errors using multi-cycle invariance information

R. Iris Bahar, Jennifer Dworak, Kundan Nepal, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Ant-Colony-Optimization based heuristic searching algorithm for cell assignment in a hybrid CMOS/nano circuits (CMOL) array

Kundan Nepal, Chong Xu, 2014, 14th IEEE International Conference on Nanotechnology.

True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors

Kundan Nepal, Daniel Hellkamp, 2019, J. Circuits Syst. Comput..

Enhancing online error detection through area-efficient multi-site implications

R. Iris Bahar, Jennifer Dworak, Kundan Nepal, 2011, 29th VLSI Test Symposium.

Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis

R. Iris Bahar, Jennifer Dworak, Kundan Nepal, 2011, 2011 Sixteenth IEEE European Test Symposium.

Detecting a trojan die in 3D stacked integrated circuits

Ping Gui, Theodore W. Manikas, Alfred L. Crouch, 2017, 2017 IEEE North Atlantic Test Workshop (NATW).

Using implications to choose tests through suspect fault identification

R. Iris Bahar, Jennifer Dworak, Kundan Nepal, 2013, TODE.

Metallic tube-tolerant ternary dynamic content-addressable memory based on carbon nanotube transistors

Kundan Nepal, Daniel Hellkamp, Kundan Nepal, 2015 .

Dynamic circuits for ternary computation in carbon nanotube based field effect transistors

Kundan Nepal, Kundan Nepal, 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

Design of a ternary static memory cell using carbon nanotube-based transistors

Kundan Nepal, Kundan Nepal, K. You, 2011 .

Carbon nanotube field effect transistor-based content addressable memory architectures

Kundan Nepal, K. You, 2012 .