Tomohiro Yoneda

发表

Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets

Chris J. Myers, Scott Little, David Walter, 2004, ATVA.

Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories

Tomohiro Yoneda, Masashi Imai, 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

Modular Synthesis of Timed Circuits using Partial Order Reduction

Chris J. Myers, Tomohiro Yoneda, Eric Mercer, 2002, Theory and Practice of Timed Systems @ ETAPS.

Using partial orders for trace theoretic verification of asynchronous circuits

Tomohiro Yoneda, Takashi Yoshikawa, T. Yoneda, 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.

Novel Implementation Method of Multiple-Way Asynchronous Arbiters

Tomohiro Yoneda, Masashi Imai, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Level oriented formal model for asynchronous circuit verification and its efficient analysis method

Chris J. Myers, Tomohiro Yoneda, Eric Mercer, 2002, 2002 Pacific Rim International Symposium on Dependable Computing, 2002. Proceedings..

Improved POSET Timing Analysis in Timed Petri Nets

Chris J. Myers, Tomohiro Yoneda, Eric Mercer, 2001 .

Interrupt handling in the loosely synchronized TMR system

Tomohiro Yoneda, Yoshihiro Tohma, Takashi Suzuoka, 1985, Systems and Computers in Japan.

Verification of Scalable Circuits with Ring Structure by Using Regular Expression

Tomohiro Yoneda, Hiroshi Toshima, 1998 .

MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures

Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, 2017, 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

Symbolic Model Checking of Analog/Mixed-Signal Circuits

Chris J. Myers, Scott Little, David Walter, 2007, 2007 Asia and South Pacific Design Automation Conference.

Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model

Chris J. Myers, Tomohiro Yoneda, Tomoya Kitai, 2003 .

A Dynamic Link-Width Optimization for Network-on-Chip

Hideharu Amano, Tomohiro Yoneda, Hiroki Matsutani, 2011, 2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications.

CTL symbolic model checking for time Petri nets using Zero-suppressed BDDs

Tomohiro Yoneda, Atsushi Takahara, Shin-ichi Minato, 1996 .

Verification of asynchronous logic circuit design using process algebra

Takashi Nanya, Tomohiro Yoneda, Atsufumi Shibayama, 1997, Systems and Computers in Japan.

A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits

Tomohiro Yoneda, Masashi Imai, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

An NoC-based evaluation platform for safety-critical automotive applications

Kenji Kise, Tomohiro Yoneda, Masashi Imai, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A task allocation method for the DTTR scheme based on task scheduling of fault patterns

Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Acceleration of timing verification method based on time petri nets

Tomohiro Yoneda, Yoshihiro Tohma, Yutaka Kondo, 1991, Systems and Computers in Japan.

Verification of Abstracted Instruction Cache of TITAC2: A Case Study

Tomohiro Yoneda, T. Yoneda, 1999, VLSI.

Conformance and mirroring for timed asynchronous circuits

Bin Zhou, Tomohiro Yoneda, Holger Schlingloff, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

Verification of asynchronous circuits based on zero‐suppressed BDDs

Tomohiro Yoneda, Koichi Masukura, Minoru Tomisaka, 2001 .

Verification of timed circuits with failure directed abstractions

Chris J. Myers, Scott Little, David Walter, 2003, Proceedings 21st International Conference on Computer Design.

Verification of asynchronous circuits based on zero-suppressed BDDs

Tomohiro Yoneda, Koichi Masukura, Minoru Tomisaka, 2001, Systems and Computers in Japan.

A Conservative Framework for Safety-Failure Checking

Chris J. Myers, Tomohiro Yoneda, Frédéric Béal, 2008, IEICE Trans. Inf. Syst..

Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip

Zhen Zhang, Chris J. Myers, Tomohiro Yoneda, 2014, FMICS.

Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets

Chris J. Myers, Scott Little, David Walter, 2011 .

An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis

Zhen Zhang, Chris J. Myers, Tomohiro Yoneda, 2016, Sci. Comput. Program..

Analysis of Petri nets with star symmetric structure

Tomohiro Yoneda, Tomoya Kitai, 2000 .

Automated Technology for Verification and Analysis, 5th International Symposium, ATVA 2007, Tokyo, Japan, October 22-25, 2007, Proceedings

Kedar S. Namjoshi, Tomohiro Yoneda, 東野輝夫, 2007, ATVA.

Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits

Chris J. Myers, Tomohiro Yoneda, Curtis A. Nelson, 2003, ICCAD.

Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits

Chris J. Myers, Tomohiro Yoneda, Denduang Pradubsuwun, 2005, IEICE Trans. Inf. Syst..

An Online Routing Mechanism with Higher Fault-Tolerance for Network-on-Chip

Tomohiro Yoneda, Vijay Holimath, Daihan Wang, 2011 .

Framework of timed trace theoretic verification revisited

Bin Zhou, Chris J. Myers, Tomohiro Yoneda, 2001, Proceedings 10th Asian Test Symposium.

Verification of Asynchronous circuits based on ZBDD

Tomohiro Yoneda, Koichi Masuikura, 1997 .

Efficient Verification of Parallel Real–Time Systems

Tomohiro Yoneda, Holger Schlingloff, H. Schlingloff, 1993, Formal Methods Syst. Des..

Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8)

Jiang Xu, Tomohiro Yoneda, Michihiro Koibuchi, 2013, NII Shonan Meet. Rep..

Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets

Chris J. Myers, Scott Little, David Walter, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits

Chris J. Myers, Tomohiro Yoneda, Curtis A. Nelson, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits

Tomohiro Yoneda, Masashi Imai, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Improving Dependability and Performance of Fully Asynchronous On-chip Networks

Tomohiro Yoneda, Masashi Imai, T. Yoneda, 2011, 2011 17th IEEE International Symposium on Asynchronous Circuits and Systems.

Distributed Algorithm for Signal Polarity Adjustment of Air-Conditioner Control Network

Tomohiro Yoneda, Chuzo Ninagawa, Koji Yokohama, 2003 .

Conformance and Mirroring for Timed System

Bin Zhou, Tomohiro Yoneda, Bernd-Holger Schlingloff, 2001 .

A self-timed implementation of Boolean functions

Tomohiro Yoneda, Märt Saarepera, 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

MTJ-based asynchronous circuits for Re-initialization free computing against power failures

Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, 2018, Microelectron. J..

Partial order reduction in verification of wheel structured parameterized circuits

Tomohiro Yoneda, Tomoya Kitai, T. Yoneda, 2001, Proceedings 2001 Pacific Rim International Symposium on Dependable Computing.

Verification of timed circuits with failure-directed abstractions

Chris J. Myers, Scott Little, David Walter, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times

Takashi Nanya, Chris J. Myers, Tomohiro Yoneda, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)

Takashi Nanya, Chris J. Myers, Tomohiro Yoneda, 2008, 2008 8th International Conference on Application of Concurrency to System Design.

BDDs vs. Zero-Suppressed BDDs: for CTL Symbolic Model Checking of Petri Nets

Tomohiro Yoneda, Atsushi Takahara, Shin-ichi Minato, 1996, FMCAD.

Timed trace theoretic verification using partial order reduction

Tomohiro Yoneda, Hiroshi Ryu, T. Yoneda, 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

Responsiveness and Timing

Nobuyuki Yamasaki, Masayoshi Takasu, Tomohiro Yoneda, 2018, VLSI Design and Test for Systems Dependability.

Verification of Bounded Delay Asynchronous Circuits with Timed Traces

Bin Zhou, Tomohiro Yoneda, Holger Schlingloff, 1999, AMAST.

Dependable real-time task execution scheme for a many-core platform

Kenji Kise, Tomohiro Yoneda, Masashi Imai, 2015, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs

Kenji Kise, Tomohiro Yoneda, Masashi Imai, 2016, 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip

Tomohiro Yoneda, Yuichi Nakamura, Hiroshi Saito, 2012, 2012 IEEE 6th International Symposium on Embedded Multicore SoCs.

N-way ring and square arbiters

Takashi Nanya, Tomohiro Yoneda, Masashi Imai, 2009, 2009 IEEE International Conference on Computer Design.

Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods

Chris J. Myers, Scott Little, David Walter, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Verification of parameterized asynchronous circuits: a case study

Tomohiro Yoneda, Märt Saarepera, Yutaka Ohtsuka, 1998, Proceedings 1998 International Conference on Application of Concurrency to System Design.

Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol

Tomohiro Yoneda, Chammika Mannakkara, 2010 .

Synthesizing Timed Circuits from High Level Specification Languages

Chris J. Myers, Tomohiro Yoneda, C. Myers, 2003 .

A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation

Takashi Nanya, Chris J. Myers, Tomohiro Yoneda, 2009, IPSJ Trans. Syst. LSI Des. Methodol..

Asynchronous pipeline controller based on early acknowledgement protocol

Tomohiro Yoneda, Chammika Mannakkara, C. Mannakkara, 2008, 2008 8th International Conference on Application of Concurrency to System Design.

Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement

Tomohiro Yoneda, Hao Zheng, Haiqiong Yao, 2010, IEEE Transactions on Computers.

Symbolic computation tree logic model checking of time Petri nets

Tomohiro Yoneda, Yasukichi Okawa, 1997 .

Synthesis of speed independent circuits based on decomposition

Chris J. Myers, Tomohiro Yoneda, Hiroomi Onda, 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..

High-Level Asynchronous Circuit Synthesis under Resource Constraints

Atsushi Matsumoto, Tomohiro Yoneda, Hiroomi Onda, 2005 .

Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation

Chris J. Myers, Tomohiro Yoneda, Tomoya Kitai, 2005, IEICE Trans. Inf. Syst..

VINAS-P: A Tool for Trace Theoretic Verification of Timed Asynchronous Circuits

Tomohiro Yoneda, 2000, CAV.

ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation

Takashi Nanya, Chris J. Myers, Tomohiro Yoneda, 2006, The Sixth IEEE International Conference on Computer and Information Technology (CIT'06).

Implementation of Interrupt Handler for Loosely-Synchronized TMR Systems

Tomohiro Yoneda, 米田友洋, 1985 .

High level synthesis of timed asynchronous circuits

Chris J. Myers, Atsushi Matsumoto, Tomohiro Yoneda, 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

Abstracted Instruction Cache of TITAC2 | As a Benchmark Circuit for Timed Asynchronous Circuit Verication

Tomohiro Yoneda, 1999 .

A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks

Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, 2016, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC).

Multi-chip NoCs for Automotive Applications

Atsushi Matsumoto, Tomohiro Yoneda, Masashi Imai, 2012, 2012 IEEE 18th Pacific Rim International Symposium on Dependable Computing.

Partial Order Reduction in Symbolic State Space Traversal Using ZBDDs

Tomohiro Yoneda, Minoru Tomisaka, 1999 .

Hazard Checking of Timed Asynchronous Circuits Revisited

Chris J. Myers, Tomohiro Yoneda, Frédéric Béal, 2007, Seventh International Conference on Application of Concurrency to System Design (ACSD 2007).

Improvement of Line Coding Overhead Targeting Both Run-Length and DC-Balance

Tomohiro Yoneda, Sarat Yoowattana, 2016, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC).

Comparing Permanent and Transient Fault Tolerance of Multiple-core based Dependable ECUs

Tomohiro Yoneda, Masashi Imai, T. Yoneda, 2015 .

Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories

Tomohiro Yoneda, Masashi Imai, 2013, IEICE Trans. Inf. Syst..

Synthesis of Timed Circuits Based on Decomposition

Chris J. Myers, Tomohiro Yoneda, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Automatic Derivation of Timing Constraints by Failure Analysis

Chris J. Myers, Tomohiro Yoneda, Tomoya Kitai, 2002, CAV.

Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols

Tomohiro Yoneda, Masashi Imai, Shinichiro Akasaka, 2018, 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits

Tomohiro Yoneda, Masashi Imai, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Verification of Scalable-Delay-Insensitive Asynchronous Circuits

Tomohiro Yoneda, Atsushi Yamazaki, Hiroshi Ryu, 1999 .

Performance Modeling and Analysis of On-chip Networks for Real-Time Applications

Tomohiro Yoneda, Masashi Imai, 2012, 2012 IEEE 18th Pacific Rim International Symposium on Dependable Computing.

Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs

Tomohiro Yoneda, Hao Zheng, Haiqiong Yao, 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

A fast timing verification method based on the independence of units

Tomohiro Yoneda, Yoshihiro Tohma, Kazutoshi Nakade, 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

7.3 Asynchronous Networks-on-Chip(7. Responsiveness, Dependable VLSI System)

Tomohiro Yoneda, Masashi Imai, 2013 .

Transition Insertion for Handling Highly Concurrent Asynchronous Specification

Atsushi Matsumoto, Tomohiro Yoneda, 2006 .

Verification of asynchronous logic circuit design using process algebra

Takashi Nanya, Tomohiro Yoneda, Atsufumi Shibayama, 1997 .

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, 2014, IEICE Trans. Inf. Syst..

Comparison of standard cell based non-linear asynchronous pipelines (VLSI設計技術)

Tomohiro Yoneda, Chammika Mannakkara, 2007 .

Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits

Chris J. Myers, Tomohiro Yoneda, Denduang Pradubsuwun, 2004, ATVA.