Mayu Aoki

Scalable 3D-FPGA using wafer-to-wafer TSV interconnect of 15 Tbps/W, 3.3 Tbps/mm2

Futoshi Furuta, Tadayuki Matsumura, Kenichi Osada, 2013, 2013 Symposium on VLSI Circuits.

Wafer-level hybrid bonding technology with copper/polymer co-planarization

Mayu Aoki, Kazuyuki Hozawa, Kenichi Takeda, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAM

Kiyoo Itoh, Mayu Aoki, Y. Nakagome, 1988 .

Void reduction in wafer bonding by simultaneously formed ventilation channels

Mayu Aoki, Kazuyuki Hozawa, Kenichi Takeda, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Chip-level TSV integration for rapid prototyping of 3D system LSIs

Futoshi Furuta, Mayu Aoki, Kazuyuki Hozawa, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

The impact of data-line interference noise on DRAM scaling

Masashi Horiguchi, Kiyoo Itoh, Mayu Aoki, 1988 .

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

Takeshi Sakata, Eiji Takeda, Mayu Aoki, 1995, IEEE J. Solid State Circuits.

A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure

Kiyoo Itoh, Mayu Aoki, Y. Nakagome, 1988 .

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

Mayu Aoki, T. Sakata, S. Kimura, 1999 .