Kazuyuki Hozawa

Scalable 3D-FPGA using wafer-to-wafer TSV interconnect of 15 Tbps/W, 3.3 Tbps/mm2

Futoshi Furuta, Tadayuki Matsumura, Kenichi Osada, 2013, 2013 Symposium on VLSI Circuits.

Wafer-level hybrid bonding technology with copper/polymer co-planarization

Mayu Aoki, Kazuyuki Hozawa, Kenichi Takeda, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

Chip-level TSV Process for Development of 3D System LSIs

Futoshi Furuta, Kazuyuki Hozawa, Kenichi Takeda, 2013 .

Evaluation of damage induced by electron beam irradiation to MOS gate pattern and method for damage-free inspection

Kazuyuki Hozawa, Jiro Inoue, Kikuo Watanabe, 2006, SPIE Advanced Lithography.

Dielectric-thickness dependence of damage induced by electron-beam irradiation of MNOS gate pattern

Kazuyuki Hozawa, Jiro Inoue, Kikuo Watanabe, 2007, SPIE Advanced Lithography.

Void reduction in wafer bonding by simultaneously formed ventilation channels

Mayu Aoki, Kazuyuki Hozawa, Kenichi Takeda, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Chip-level TSV integration for rapid prototyping of 3D system LSIs

Futoshi Furuta, Mayu Aoki, Kazuyuki Hozawa, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.