S. Kubicek

Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing

B. Parvais, S. Brebels, B. Govoreanu, 2021, 2021 Symposium on VLSI Circuits.

Uniform Spin Qubit Devices with Tunable Coupling in an All-Silicon 300 mm Integrated Process

L. Goux, B. Govoreanu, F. A. Mohiyaddin, 2021, 2021 Symposium on VLSI Circuits.

Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins

L. Witters, N. Collaert, H. Bender, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Scaling of high-k dielectrics towards sub-1nm EOT

S. De Gendt, D. Pique, S. Van Elshocht, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technology

C. Ortolland, A. Akheyar, T. Chiarella, 2006, 2009 Symposium on VLSI Technology.

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

D. Mocuta, R. Ritzenthaler, W. Vandervorst, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Standard cell level parasitics assessment in 20nm BPL and 14nm BFF

A. Mercha, D. Verkest, M. Badaroglu, 2012, International Electron Devices Meeting.

PVD-HIGH-K GATE DIELECTRICS WITH FUSI GATE AND INFLUENCE OF PDA TREATMENT ON ON-STATE DRIVE CURRENT

Serge Biesemans, Shigenori Hayashi, S. Kubicek, 2006 .