Peter Wohl

发表

X-tolerant compression and application of scan-atpg patterns in a bist architecture

Minesh B. Amin, Peter Wohl, John A. Waicukauski, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Increasing Scan Compression by Using X-chains

Peter Wohl, John A. Waicukauski, Frederic Neuveux, 2008, 2008 IEEE International Test Conference.

Using Verilog simulation libraries for ATPG

Peter Wohl, John A. Waicukauski, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

Two-level compression through selective reseeding

Peter Wohl, John A. Waicukauski, Frederic Neuveux, 2013, 2013 IEEE International Test Conference (ITC).

Hybrid selector for high-X scan compression

Peter Wohl, John A. Waicukauski, Frederic Neuveux, 2012, 2012 IEEE International Test Conference.

Extracting gate-level networks from simulation tables

Peter Wohl, John A. Waicukauski, J. Waicukauski, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Using ATPG for clock rules checking in complex scan designs

Peter Wohl, John A. Waicukauski, J. Waicukauski, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

Fully X-tolerant combinational scan compression

Peter Wohl, John A. Waicukauski, Sanjay Ramnath, 2007, 2007 IEEE International Test Conference.

A parallel processing approach to incremental conceptual clustering

Thomas W. Christopher, Peter Wohl, T. Christopher, 1991, [1991] Proceedings. The Fifth International Parallel Processing Symposium.

Enhancing testability by structured partial scan

Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

Scalable selector architecture for X-tolerant deterministic BIST

Peter Wohl, John A. Waicukauski, Sanjay Patel, 2004, Proceedings. 41st Design Automation Conference, 2004..

Efficient compression and application of deterministic patterns in a logic BIST architecture

Minesh B. Amin, Peter Wohl, John A. Waicukauski, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

SIMD Neural Net Mapping on MIMD Architectures

Thomas W. Christopher, Peter Wohl, 1990, ICPP.

A unified interface for scan test generation based on STIL

Peter Wohl, John A. Waicukauski, 1997, Proceedings International Test Conference 1997.

Efficient compression of deterministic patterns into multiple PRPG seeds

Rohit Kapur, Thomas W. Williams, Peter Wohl, 2005, IEEE International Conference on Test, 2005..

Minimizing the Impact of Scan Compression

Rohit Kapur, Thomas W. Williams, Peter Wohl, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

DFT MAX and Power

Rohit Kapur, Thomas W. Williams, Peter Wohl, 2007, J. Low Power Electron..

XLBIST: X-Tolerant Logic BIST

Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, 2018, 2018 IEEE International Test Conference (ITC).

Effective diagnostics through interval unloads in a BIST environment

Peter Wohl, John A. Waicukauski, Sanjay Patel, 2002, DAC '02.

A distributed-multicore hybrid ATPG system

Peter Wohl, X. Cai, 2013, 2013 IEEE International Test Conference (ITC).

Analysis and design of optimal combinational compactors [logic test]

Peter Wohl, Leendert M. Huisman, P. Wohl, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Testing "untestable" faults in three-state circuits

Peter Wohl, John A. Waicukauski, Matthew Graf, 1996, Proceedings of 14th VLSI Test Symposium.

MIMD implementation of neural networks through pipelined, parallel communication trees

Thomas W. Christopher, Peter Wohl, 1991, [Proceedings] Third International Conference on Tools for Artificial Intelligence - TAI 91.

Achieving extreme scan compression for SoC Designs

Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, 2014, 2014 International Test Conference.

Program Committee

Michael S. Hsiao, Irith Pomeranz, Nur A. Touba, 2006, WOWMOM.

Analysis and Design of Optimal Combinational Compactors

Peter Wohl, Leendert Huisman, 2003 .

Designing Conceptual Clustering for Parallel Implementation

Thomas W. Christopher, Peter Wohl, 1992, ICPP.

Hierarchical compactor design for diagnosis in deterministic logic BIST

Peter Wohl, John A. Waicukauski, Sanjay Patel, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Efficiency through Reduced Communication in Message Passing Simulation of Neural Networks

Peter Wohl, 1993, Int. J. Artif. Intell. Tools.

Highly efficient parallel ATPG based on shared memory

Peter Wohl, John A. Waicukauski, X. Cai, 2010, 2010 IEEE International Test Conference.

Automated Design and Insertion of Optimal One-Hot Bus Encoders

Peter Wohl, John A. Waicukauski, Sanjay Patel, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Fully X-tolerant, very high scan compression

Peter Wohl, John A. Waicukauski, Frederic Neuveux, 2010, Design Automation Conference.

Defining ATPG rules checking in STIL

Peter Wohl, John A. Waicukauski, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Test generation for ultra-large circuits using ATPG constraints and test-pattern templates

Peter Wohl, John A. Waicukauski, J. Waicukauski, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

P1450.1: STIL for the simulation environment

Peter Wohl, Nathan Biggs, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Output in still, input in still

Peter Wohl, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

A new paradigm for synthesis of linear decompressors

Peter Wohl, John A. Waicukauski, Emil Gizdarski, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Parallel Conceptual Clustering through Message-Driven Computing

Thomas W. Christopher, Peter Wohl, 1991, ICPP.

Fault sharing in a copy-on-write based ATPG system

Peter Wohl, X. Cai, Daniel Martin, 2014, 2014 International Test Conference.

Increasing PRPG-based compression by delayed justification

Peter Wohl, John A. Waicukauski, T. Finklea, 2010, 2010 IEEE International Test Conference.

Design of compactors for signature-analyzers in built-in self-test

Thomas W. Williams, Peter Wohl, John A. Waicukauski, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).