Nicola Da Dalt

发表

Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters

Dmytro Cherniak, Michael Aichner, Roberto Nonis, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider

Dmytro Cherniak, Roberto Nonis, Nicola Da Dalt, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique

Luca Selmi, Pierpaolo Palestri, Nicola Da Dalt, 2015, Int. J. Circuit Theory Appl..

Jitter Noise of Sampled Multitone Signals

Martin Clara, Nicola Da Dalt, 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS

Roberto Nonis, Nicola Da Dalt, Werner Grollitsch, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture

Luca Selmi, Pierpaolo Palestri, Roberto Nonis, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

On the jitter requirements of the sampling clock for analog-to-digital converters

Andreas Wiesbauer, Nicola Da Dalt, Christoph Sandner, 2002 .

Techniques for the Analysis of Digital Bang‐Bang PLLs

Nicola Da Dalt, 2010 .

Understanding Jitter and Phase Noise: A Circuits and Systems Perspective

Ali Sheikholeslami, Nicola Da Dalt, N. D. Dalt, 2018 .

An Analysis of Phase Noise in Realigned VCOs

Nicola Da Dalt, N. D. Dalt, 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs

Nicola Da Dalt, N. D. Dalt, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

High-Speed Communications on Four Wheels: What?s in Your Next Car? [Conference Reports]

Ajith Amerasekera, Nicola Da Dalt, 2013 .

ES3: High-speed communications on 4 wheels: What's in your next car?

Ajith Amerasekera, Nicola Da Dalt, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS

Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani, 2009, 2009 Proceedings of ESSCIRC.

An all-digital PLL using random modulation for SSC generation in 65nm CMOS

Nicola Da Dalt, Peter Pridnig, Werner Grollitsch, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 0.06 mm$^{2}$ 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS

Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani, 2010, IEEE Journal of Solid-State Circuits.

A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS

Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani, 2010, 2010 Proceedings of ESSCIRC.

Improved Modeling of Intersymbol Interference in High Speed Serial Links

Andrea Cristofoli, Pierpaolo Palestri, Luca Selmi, 2012 .

A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs

Nicola Da Dalt, 2005, IEEE Trans. Circuits Syst. I Regul. Pap..

Effect of jitter on asynchronous sampling with finite number of samples

Nicola Da Dalt, 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming

Christian Vogel, Nicola Da Dalt, Stefan Mendel, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture

Dmytro Cherniak, Roberto Nonis, Nicola Da Dalt, 2013, IEEE Journal of Solid-State Circuits.

Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs

Luca Selmi, Pierpaolo Palestri, Roberto Nonis, 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

LDO with distributed output means

Roberto Nonis, Nicola Da Dalt, 2010 .

Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation

Nicola Da Dalt, N. D. Dalt, 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.