Kuo-Liang Cheng

发表

Simulation-based test algorithm generation for random access memories

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Design High Speed Spindle Cooling System Using Novel Solid-Fluid Coupling Heat Transfer Computational Scheme

De-Shin Liu, Kuo-Liang Cheng, Zhen-Wei Zhuang, 2011 .

An SOC test integration platform and its industrial realization

Cheng-Wen Wu, Chih-Tsun Huang, Jing-Reng Huang, 2004 .

Error catch and analysis for semiconductor memories using March tests

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories

Cheng-Wen Wu, Ming-Fu Tsai, Kuo-Liang Cheng, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Test scheduling and test access architecture optimization for system-on-chip

Youn-Long Lin, Cheng-Wen Wu, Chih-Tsun Huang, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Flash memory built-in self-test using March-like algorithms

Jen-Chieh Yeh, Cheng-Wen Wu, Chih-Tsun Huang, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

Test and diagnosis of word-oriented multiport memories

Cheng-Wen Wu, Chih-Tsun Huang, Kuo-Liang Cheng, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

March-based RAM diagnosis algorithms for stuck-at and coupling faults

Jin-Fu Li, Cheng-Wen Wu, Chih-Tsun Huang, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Fault simulation and test algorithm generation for random accessmemories

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Test scheduling of BISTed memory cores for SoC

Youn-Long Lin, Cheng-Wen Wu, Chih-Tsun Huang, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Automatic generation of memory built-in self-test cores for system-on-chip

Jen-Chieh Yeh, Cheng-Wen Wu, Chih-Tsun Huang, 2001, Proceedings 10th Asian Test Symposium.

FAME: A Fault-Pattern Based Memory Failure Analysis Framework

Cheng-Wen Wu, Chih-Tsun Huang, Jih-Nung Lee, 2003, ICCAD 2003.

FAME: A Fault-Pattern Based Memory Failure Analysis Framework

Cheng-Wen Wu, Chih-Tsun Huang, Jih-Nung Lee, 2003, ICCAD.

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms

Jen-Chieh Yeh, Cheng-Wen Wu, Yung-Fa Chou, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Design and test of a scalable security processor

Cheng-Wen Wu, Chih-Tsun Huang, Chen-Hsing Wang, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Fault pattern oriented defect diagnosis for memories

Hong-Tzer Yang, Cheng-Wen Wu, Chih-Tsun Huang, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

RAMSES-FT: a fault simulator for flash memory testing and diagnostics

Jen-Chieh Yeh, Cheng-Wen Wu, Chih-Tsun Huang, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

STEAC: A Platform for Automatic SOC Test Integration

Cheng-Wen Wu, Jing-Reng Huang, Chih-Yen Lo, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Simulation-based test algorithm generation and port scheduling for multi-port memories

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 2001, DAC '01.

Design and test of a scalable security processor

Cheng-Wen Wu, Chih-Tsun Huang, Chen-Hsing Wang, 2005, ASP-DAC.

An SOC test integration platform and its industrial realization

Chih-Tsun Huang, Jing-Reng Huang, Chih-Yen Lo, 2004, 2004 International Conferce on Test.

Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories

Cheng-Wen Wu, Ming-Fu Tsai, Kuo-Liang Cheng, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.