Malte Baesler

An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier

Malte Baesler, Sven-Ole Voigt, Thomas Teufel, 2010, 2010 International Conference on Field Programmable Logic and Applications.

FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers

Malte Baesler, Sven-Ole Voigt, Thomas Teufel, 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

A radix-10 digit recurrence division unit with a constant digit selection function

Malte Baesler, Sven-Ole Voigt, Thomas Teufel, 2010, 2010 IEEE International Conference on Computer Design.

FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier

Malte Baesler, Thomas Teufel, 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

Dynamically reconfigurable dataflow architecture for high-performance digital signal processing

Malte Baesler, Sven-Ole Voigt, Thomas Teufel, 2010, J. Syst. Archit..

A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA

Malte Baesler, Sven-Ole Voigt, Thomas Teufel, 2010, Int. J. Reconfigurable Comput..

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Malte Baesler, Sven-Ole Voigt, 2013, Int. J. Reconfigurable Comput..

FPGA implementation of a decimal floating-point co-processor with accurate scalar product unit

Malte Baesler, 2012 .