J. Stine

发表

FreePDK: An Open-Source Variation-Aware Design Kit

Paul D. Franzon, Michael Bucher, Fred Love, 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

Floating-Point Extension for Containing Error in the RISC-V Architecture

J. Stine, Alexander Underwood, Tuan D. Nguyen, 2019 .

A Reconfigurable Architecture for Improvement and Optimization of Advanced Encryption Standard Hardware

J. Stine, Ryan Swann, 2021, 2021 55th Asilomar Conference on Signals, Systems, and Computers.

Implementation of High Performance IEEE 754-Posit Conversion Hardware

J. Stine, Brett Mathis, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS).

Variations on truncated multiplication

James E. Stine, Oliver M. Duverne, J. Stine, 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

Modified booth truncated multipliers

James E. Stine, Alok A. Katkar, J. Stine, 2004, GLSVLSI '04.

Accurate function approximations by symmetric table lookup and addition

Michael J. Schulte, James E. Stine, J. Stine, 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

Evaluation of a Modular Approach to AES Hardware Architecture and Optimization

J. Stine, Ryan Swann, 2023, Journal of Signal Processing Systems.

Parallel Prefix Ling Structures for Modulo 2^n-1 Addition

Jun Chen, James. E. Stine, J. Stine, 2009, 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors.

OpenRAM: An open-source memory compiler

Bin Wu, Brian Chen, James E. Stine, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

The Symmetric Table Addition Method for Accurate Function Approximation

Michael J. Schulte, James E. Stine, J. Stine, 1999, J. VLSI Signal Process..

A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS

James E. Stine, Matthew R. Guthaus, Samira Ataei, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

Reduced power dissipation through truncated multiplication

Michael J. Schulte, James E. Stine, J. Stine, 1999, Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design.

Decimal partial product generation architectures

J.E. Stine, I.D. Castellanos, J. Stine, 2008, 2008 51st Midwest Symposium on Circuits and Systems.

Compressor trees for decimal partial product reduction

James E. Stine, Ivan D. Castellanos, J. Stine, 2008, GLSVLSI '08.

A 64-bit Decimal Floating-Point Comparator

James E. Stine, Ivan D. Castellanos, J. Stine, 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

A combined two's complement and floating-point comparator

Michael J. Schulte, James E. Stine, J. Stine, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A combined interval and floating-point comparator

James E. Stine, C. M. Kaas, J. Stine, 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

Sustainable IC design and fabrication

Alex K. Jones, Erik Brunvand, Donald Kline, 2017, 2017 Eighth International Green and Sustainable Computing Conference (IGSC).

Variable-correction truncated floating point multipliers

J. Stine, J.E. Stine, M.J. Schulte, 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

A Case for Interval Hardware on Superscalar Processors

Michael J. Schulte, James E. Stine, J. Stine, 2001 .

Evaluating the Impact of Accurate Branch Prediction on Interval Software

Michael J. Schulte, James E. Stine, Ahmet Akkas, 2001 .

Strategies for VLSI implementations of finite field inversion algorithms

J. Stine, N. Jachimiec, N. Iliev, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

A combined IEEE half and single precision floating point multipliers for deep learning

James E. Stine, Tuan D. Nguyen, J. Stine, 2017, 2017 51st Asilomar Conference on Signals, Systems, and Computers.