K. Chang

发表

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Onur Mutlu, Gennady Pekhimenko, Vivek Seshadri, 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study

Onur Mutlu, Aditya Agrawal, Saugata Ghose, 2018, SIGMETRICS.

What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study

O. Mutlu, Donghyuk Lee, K. Chang, 2018, PERV.

Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms pdf

Onur Mutlu, Aditya Agrawal, Abhijith Kashyap, 2017, ArXiv.

HAT: Heterogeneous Adaptive Throttling for On-Chip Networks

Kevin Kai-Wei Chang, Rachata Ausavarungnirun, Chris Fallin, 2012, 2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing.

Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins pdf

Onur Mutlu, Samira Manabi Khan, Gennady Pekhimenko, 2018, ArXiv.

Improving DRAM performance by parallelizing refreshes with accesses

Onur Mutlu, Alaa R. Alameldeen, Chris Wilkerson, 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems

Kevin Kai-Wei Chang, Rachata Ausavarungnirun, Onur Mutlu, 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

Understanding and Improving the Latency of DRAM-Based Memory Systems pdf

Kevin K. Chang, K. Chang, 2017, ArXiv.

DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators

Kevin Kai-Wei Chang, Onur Mutlu, Lavanya Subramanian, 2016, ACM Trans. Archit. Code Optim..

Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation

Onur Mutlu, Samira Manabi Khan, Saugata Ghose, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms

O. Mutlu, Donghyuk Lee, K. Chang, 2017, SIGMETRICS.

SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies

Onur Mutlu, Oguz Ergin, Samira Manabi Khan, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization

Onur Mutlu, Tianshi Li, Samira Manabi Khan, 2016, SIGMETRICS.

Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM

Onur Mutlu, Saugata Ghose, Moinuddin K. Qureshi, 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

What Your DRAM Power Models Are Not Telling You

Onur Mutlu, Aditya Agrawal, Saugata Ghose, 2018, Proc. ACM Meas. Anal. Comput. Syst..

Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency pdf

Onur Mutlu, Aditya Agrawal, Abhijith Kashyap, 2018, ArXiv.

SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure pdf

Onur Mutlu, Oguz Ergin, Samira Manabi Khan, 2018, ArXiv.

Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips pdf

Onur Mutlu, Tianshi Li, Gennady Pekhimenko, 2018, ArXiv.

Reducing DRAM Refresh Overheads with Refresh-Access Parallelism pdf

Onur Mutlu, Alaa R. Alameldeen, Chris Wilkerson, 2018, ArXiv.

High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems pdf

Rachata Ausavarungnirun, Onur Mutlu, Gabriel H. Loh, 2018, ArXiv.

Understanding Reduced-Voltage Operation in Modern DRAM Devices

Onur Mutlu, Aditya Agrawal, Abhijith Kashyap, 2017, Proc. ACM Meas. Anal. Comput. Syst..

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Gennady Pekhimenko, Vivek Seshadri, O. Mutlu, 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate

Reetuparna Das, Kevin Kai-Wei Chang, Rachata Ausavarungnirun, 2016, Parallel Comput..

Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing pdf

Reetuparna Das, Kevin Kai-Wei Chang, Rachata Ausavarungnirun, 2016, ArXiv.

Adaptive-Latency DRAM (AL-DRAM) pdf

Kevin Kai-Wei Chang, Onur Mutlu, Samira Manabi Khan, 2016, ArXiv.

Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips

Gennady Pekhimenko, O. Mutlu, Donghyuk Lee, 2018, arXiv.org.

LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency pdf

Onur Mutlu, Saugata Ghose, Moinuddin K. Qureshi, 2018, ArXiv.

Understanding Reduced-Voltage Operation in Modern DRAM Devices

MutluOnur, LeeDonghyuk, GhoseSaugata, 2017, SIGMETRICS.

Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM

Moinuddin K. Qureshi, Prashant J. Nair, O. Mutlu, 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).