S. Sawada

On the retention time distribution of dynamic random access memory (DRAM)

T. Hamamoto, S. Sugiura, S. Sawada, 1998 .

Reduction of Signal Voltage of DRAM Cell Induced by Discharge of Trapped Charges in Nano-Meter Thick Dual Dielectric Film (SiO2/Si3N4)

S. Sawada, K. Toita, J. Kumagai, 1990 .

Reduction of signal voltage of DRAM cell induced by discharge of trapped charges in nano-meter thick dual dielectric film (SiO/sub 2//Si/sub 3/N/sub 4/)

S. Sawada, K. Toita, J. Kumagai, 1990, 28th Annual Proceedings on Reliability Physics Symposium.

Well concentration: a novel scaling limitation factor derived from DRAM retention time and its modeling

Takeshi Hamamoto, S. Sugiura, S. Sawada, 1995, Proceedings of International Electron Devices Meeting.

Measurement of intrinsic capacitance of lightly doped drain (LDD) MOSFET's

Y. Matsumoto, O. Ozawa, H. Ishiuchi, 1985, IEEE Transactions on Electron Devices.

Degradation of Thin-Gate Mosfet's under High Electric Field Stress

S. Sawada, H. Ishiuchi, O. Ozawa, 1982, 20th International Reliability Physics Symposium.

Analytical model for oblique ion reflection at the Si surface

S. Sawada, S. Shinozaki, H. Ishiuchi, 1988 .

High performance deep submicron buried channel PMOSFET using P/sup +/ poly-Si spacer induced self-aligned ultra shallow junctions

S. Sawada, H. Ishiuchi, F. Matsuoka, 1992, 1992 International Technical Digest on Electron Devices Meeting.