S. Keckler

发表

SCNN: An accelerator for compressed-sparse convolutional neural networks

William J. Dally, Antonio Puglielli, Brucek Khailany, 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks

Stephen W. Keckler, Niladrish Chatterjee, Mike O'Connor, 2017, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Measuring Experimental Error in Microprocessor Simulation

Doug Burger, Stephen W. Keckler, Rajagopalan Desikan, 2001, ISCA 2001.

Virtualizing Deep Neural Networks for Memory-Efficient Neural Network Design pdf

Natalia Gimelshein, Jason Clemons, Stephen W. Keckler, 2016, ArXiv.

Toggle-Aware Bandwidth Compression for GPUs

Gennady Pekhimenko, O. Mutlu, T. Mowry, 2015 .

Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems

Onur Mutlu, Stephen W. Keckler, Gwangsun Kim, 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

Universal mechanisms for data-parallel architectures

Karthikeyan Sankaralingam, Stephen W. Keckler, Doug Burger, 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

Static placement, dynamic issue (SPDI) scheduling for EDGE architectures

Kathryn S. McKinley, Calvin Lin, Doug Burger, 2004, Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004..

Network-on-chip implementation and performance improvement through workload characterization and congestion awareness

Stephen W. Keckler, Paul V. Gratz, S. Keckler, 2008 .

GPU Domain Specialization via Composable On-Package Architecture pdf

David W. Nellans, Stephen W. Keckler, Niladrish Chatterjee, 2021, ACM Trans. Archit. Code Optim..

The impact of delay on the design of branch predictors

Daniel A. Jiménez, S. Keckler, C. Lin, 2000, Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.

Arbitrary Modulus Indexing

Jeffrey R. Diamond, Donald S. Fussell, Stephen W. Keckler, 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

Static energy reduction techniques for microprocessor caches

Vikas Agarwal, Doug Burger, Stephen W. Keckler, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

A compile-time managed multi-level register file hierarchy

William J. Dally, Stephen W. Keckler, Mark Gebhart, 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

SCNN

W. Dally, A. Parashar, Minsoo Rhu, 2017 .

Research Challenges for On-Chip Interconnection Networks

William J. Dally, John D. Owens, Ron Ho, 2007, IEEE Micro.

MATERIAL PROPERTIES OF LASER POWDER BED FUSION PROCESSED 316L STAINLESS STEEL

S. Keckler, 2018 .

Optimizing Selective Protection for CNN Resilience

Christopher W. Fletcher, Naresh R Shanbhag, Michael B. Sullivan, 2021, 2021 IEEE 32nd International Symposium on Software Reliability Engineering (ISSRE).

The Mmmachine Multicomputer

William J. Dally, Stephen W. Keckler, Nicholas P. Carter, 1995 .

Gpus and the Future of Parallel Computing This Article Discusses the Capabilities of State-of-the Art Gpu-based High- Throughput Computing Systems and Considers the Challenges to Scaling Single-chip Parallel-computing Systems, Highlighting High-impact Areas That the Computing Research Community Can

W. Dally, B. Khailany, S. Keckler, 2011 .

The Importance of Locality in Scheduling and Load Balancing for Multiprocessors

S. Keckler, 1994 .

Topology-Aware quality-of-service support in highly integrated chip multiprocessors

Onur Mutlu, Stephen W. Keckler, Boris Grot, 2010, ISCA'10.

A characterization of speech recognition on modern computer systems

S. Keckler, D. Burger, K. Agaram, 2001, Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization. WWC-4 (Cat. No.01EX538).

Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings

Michael B. Sullivan, Donghyuk Lee, S. Keckler, 2022, 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Stitch-X: An Accelerator Architecture for Exploiting Unstructured Sparsity in Deep Neural Networks

A. Parashar, S. Keckler, Zhengya Zhang, 2018 .

Kayotee: A Fault Injection-based System to Assess the Safety and Reliability of Autonomous Vehicles to Faults and Errors pdf

Ravishankar K. Iyer, Stephen W. Keckler, Zbigniew Kalbarczyk, 2019, ArXiv.

Scalable hardware memory disambiguation for high-ILP processors

C. R. Moore, S. Keckler, R. Desikan, 2004, IEEE Micro.

GPU snapshot: checkpoint offloading for GPU-dense systems

Mattan Erez, Stephen W. Keckler, Michael B. Sullivan, 2019, ICS.

The Memory Behavior of Data Structures in C SPEC CPU 2000 Benchmarks

S. Keckler, K. McKinley, Calvin Lin, 2006 .

Simba

C. T. Gray, W. Dally, Rangharajan Venkatesan, 2019, Communications of the ACM.

Architecture for High Performance Systems

Vikas Agarwal, Karthikeyan Sankaralingam, Doug Burger, 2003 .

The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

S. Keckler, N. Jouppi, D. Burger, 2002, Proceedings 29th Annual International Symposium on Computer Architecture.

A Routing Network for the Grid Processor Architecture

Doug Burger, Stephen W. Keckler, Vincent Ajay Singh, 2003 .

Assessment of MRAM Technology Characteristics and Architectures

Doug Burger, Stephen W. Keckler, Rajagopalan Desikan, 2001 .

The Effect of Technology Scaling on Microarchitectural Structures

Vinod K. Agarwal, Doug Burger, Stephen W. Keckler, 2000 .

Composable Lightweight Processors

Madhu Saravana Sibi Govindan, S. Keckler, D. Burger, 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

Analysis of the TRIPS Architecture by Dipak Chand Boyed

S. Keckler, 2004 .

Multitasking workload scheduling on flexible core chip multiprocessors

S. Keckler, D. Burger, Changkyu Kim, 2008, CARN.

Measuring experimental error in microprocessor simulation

S. Keckler, R. Desikan, D. Burger, 2001, Proceedings 28th Annual International Symposium on Computer Architecture.

Maximizing Area Efficiency for Single-Chip Server Processors

S. Keckler, D. Burger, Jaehyuk Huh, 2001 .

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

C. R. Moore, S. Keckler, K. Sankaralingam, 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..

Composable Lightweight Processors

Madhu Saravana Sibi Govindan, S. Keckler, D. Burger, 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

TRIPS Application Binary Interface (ABI) Manual

Kathryn S. McKinley, Doug Burger, Stephen W. Keckler, 2005 .

Exploiting Temporal Data Diversity for Detecting Safety-critical Faults in AV Compute Systems

Michael B. Sullivan, S. Keckler, Saurabh Jha, 2022, 2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN).

Energy-Efficient Data Compression for GPU Memory Systems

Gennady Pekhimenko, O. Mutlu, T. Mowry, 2014 .

Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications

Rangharajan Venkatesan, S. Keckler, Jason Clemons, 2022, arXiv.org.

Scaling the Power Wall: A Path to Exascale

William J. Dally, Justin Luitjens, David W. Nellans, 2014, SC14: International Conference for High Performance Computing, Networking, Storage and Analysis.

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

William J. Dally, Brucek Khailany, Stephen G. Tell, 2019, 2019 Symposium on VLSI Circuits.

Evolution of the Graphics Processing Unit (GPU)

William J. Dally, Stephen W. Keckler, David B. Kirk, 2021, IEEE Micro.

NVBit: A Dynamic Binary Instrumentation Framework for NVIDIA GPUs

Oreste Villa, Stephen W. Keckler, Mark Stephenson, 2019, MICRO.

A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

William J. Dally, Yanqing Zhang, Brucek Khailany, 2020, IEEE Journal of Solid-State Circuits.

Timeloop: A Systematic Approach to DNN Accelerator Evaluation

Brucek Khailany, Stephen W. Keckler, Joel S. Emer, 2019, 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design

Natalia Gimelshein, Jason Clemons, Stephen W. Keckler, 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

TRIPS: A distributed explicit data graph execution (EDGE) microprocessor

Doug Burger, Madhu Saravana Sibi Govindan, Steve Keckler, 2007, 2007 IEEE Hot Chips 19 Symposium (HCS).

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture

William J. Dally, Yanqing Zhang, Brucek Khailany, 2019, MICRO.

Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration

Jason Clemons, Stephen W. Keckler, Joel S. Emer, 2019, ASPLOS.

GPUs and the Future of Parallel Computing

William J. Dally, Michael Garland, David Glasco, 2011, IEEE Micro.

Making Convolutions Resilient Via Algorithm-Based Error Detection Techniques pdf

Stephen W. Keckler, Michael B. Sullivan, Timothy Tsai, 2020, IEEE Transactions on Dependable and Secure Computing.

NVBitFI: Dynamic Fault Injection for GPUs

Stephen W. Keckler, Oreste Villa, Timothy Tsai, 2021, 2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN).

HarDNN: Feature Map Vulnerability Evaluation in CNNs pdf

Charbel Sakr, Pavlo Molchanov, Sarita V. Adve, 2020, ArXiv.

Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications

Guanpeng Li, Karthik Pattabiraman, Stephen W. Keckler, 2017, SC17: International Conference for High Performance Computing, Networking, Storage and Analysis.

SASSIFI: An architecture-level fault injection tool for GPU application resilience evaluation

Stephen W. Keckler, Mark Stephenson, Joel S. Emer, 2017, 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Simba

C. T. Gray, W. Dally, Rangharajan Venkatesan, 2021, Commun. ACM.

Energy-efficient mechanisms for managing thread context in throughput processors

William J. Dally, Kevin Skadron, Daniel R. Johnson, 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

SNAP: A 1.67 — 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS

Chester Liu, Stephen W. Keckler, Zhengya Zhang, 2019, 2019 Symposium on VLSI Circuits.

Buddy Compression: Enabling Larger Memory for Deep Learning and HPC Workloads on GPUs

David W. Nellans, Mattan Erez, Stephen W. Keckler, 2019, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).

High performance dense linear algebra on a spatially distributed processor

Robert A. van de Geijn, Jeffrey R. Diamond, Doug Burger, 2008, PPoPP.

The M-machine multicomputer

William J. Dally, Stephen W. Keckler, Nicholas P. Carter, 1997, Proceedings of the 28th Annual International Symposium on Microarchitecture.

The M-Machine multicomputer

W. Dally, S. Keckler, Marco Fillo, 1995, MICRO 28.

Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications

Mahmut T. Kandemir, Chita R. Das, Stephen W. Keckler, 2014, GPGPU@ASPLOS.

Generating and Characterizing Scenarios for Safety Testing of Autonomous Vehicles

Zahra Ghodsi, Siddharth Garg, Iuri Frosio, 2021, 2021 IEEE Intelligent Vehicles Symposium (IV).

Zhuyi: perception processing rate estimation for safety in autonomous vehicles

Michael B. Sullivan, S. Keckler, V. Reddi, 2022, DAC.

Exploiting microarchitectural redundancy for defect tolerance

Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, 2003, 2012 IEEE 30th International Conference on Computer Design (ICCD).

ML-Based Fault Injection for Autonomous Vehicles: A Case for Bayesian Fault Injection

Ravishankar K. Iyer, Zbigniew T. Kalbarczyk, Stephen W. Keckler, 2019, 2019 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN).

A patch memory system for image processing and computer vision

Chih-Chi Cheng, Jason Clemons, Iuri Frosio, 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Hardware support for fast capability-based addressing

William J. Dally, Stephen W. Keckler, Nicholas P. Carter, 1994, ASPLOS VI.

Anatomy of GPU Memory System for Multi-Application Execution

Mahmut T. Kandemir, Chita R. Das, Stephen W. Keckler, 2015, MEMSYS.

Training Long Short-Term Memory With Sparsified Stochastic Gradient Descent

Yuan Xie, Jason Clemons, Stephen W. Keckler, 2017 .

Architecting an Energy-Efficient DRAM System for GPUs

William J. Dally, Daniel R. Johnson, Stephen W. Keckler, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

CLARA: Circular Linked-List Auto and Self Refresh Architecture

Aditya Agrawal, Stephen W. Keckler, Niladrish Chatterjee, 2016, MEMSYS.

Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor

William J. Dally, Brucek Khailany, Stephen W. Keckler, 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems

Onur Mutlu, Stephen W. Keckler, Gwangsun Kim, 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

MAGNet: A Modular Accelerator Generator for Neural Networks

William J. Dally, Brucek Khailany, Jason Clemons, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Characterizing and Mitigating Soft Errors in GPU DRAM

Michael B. Sullivan, Donghyuk Lee, S. Keckler, 2021, IEEE Micro.

Flexible software profiling of GPU architectures

David W. Nellans, Daniel R. Johnson, Stephen W. Keckler, 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

Unlocking bandwidth for GPUs in CC-NUMA systems

Thomas F. Wenisch, David W. Nellans, Stephen W. Keckler, 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference

Stephen W. Keckler, Zhengya Zhang, Yakun Sophia Shao, 2021, IEEE Journal of Solid-State Circuits.

Modeling the effect of technology trends on the soft error rate of combinational logic

Lorenzo Alvisi, Doug Burger, Stephen W. Keckler, 2002, Proceedings International Conference on Dependable Systems and Networks.

TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP

Jaehyuk Huh, Karthikeyan Sankaralingam, Doug Burger, 2004, TACO.

Kilo-NOC: A heterogeneous network-on-chip architecture for scalability and service guarantees

Onur Mutlu, Stephen W. Keckler, Boris Grot, 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

Netrace: dependency-driven trace-based network-on-chip simulation

Stephen W. Keckler, Boris Grot, Joel Hestness, 2010, NoCArc '10.

cuCatch: A Debugging Tool for Efficiently Catching Memory Safety Violations in CUDA Applications

S. Keckler, A. Jaleel, M. Stephenson, 2023 .

Cooperative Profile Guided Optimizations

Stephen W. Keckler, Ram Rangan, Mark Stephenson, 2021, Comput. Graph. Forum.

Clock rate versus IPC: the end of the road for conventional microarchitectures

Vikas Agarwal, Doug Burger, Stephen W. Keckler, 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

Towards high performance paged memory for GPUs

David W. Nellans, Stephen W. Keckler, Mark Stephenson, 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Designing Efficient Heterogeneous Memory Architectures

Alex Ramírez, David W. Nellans, Oreste Villa, 2015, IEEE Micro.

Page Placement Strategies for GPUs within Heterogeneous Memory Systems

Stephen W. Keckler, Mark Stephenson, Neha Agarwal, 2015, ASPLOS.

Reconciling performance and programmability in networking systems

Harrick M. Vin, Stephen W. Keckler, Jayaram Mudigonda, 2007, SIGCOMM '07.

Multicore Processors and Systems

Kunle Olukotun, H. Peter Hofstee, Stephen W. Keckler, 2009, Integrated Circuits and Systems.

Massively Multithreaded Computing Systems

Stephen W. Keckler, Steven K. Reinhardt, S. Keckler, 2012, Computer.

The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline

William J. Dally, Stephen W. Keckler, Nicholas P. Carter, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Polymorphous architectures: a unified approach for extracting concurrency of different granularities

Karthikeyan Sankaralingam, Stephen W. Keckler, S. Keckler, 2006 .

A design space evaluation of grid processor architectures

R. Nagarajan, K. Sankaralingam, D. Burger, 2001, Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34.

Techniques to improve the hard and soft error reliability of distributed architectures

Stephen W. Keckler, Premkishore Shivakumar, S. Keckler, 2007 .

Regional congestion awareness for load balance in networks-on-chip

Stephen W. Keckler, Paul Gratz, Boris Grot, 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

Microprocessor pipeline energy analysis

D. Burger, H. Hanson, C. R. Moore, 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

Optimizing Software-Directed Instruction Replication for GPU Error Detection

Stephen W. Keckler, Abdulrahman Mahmoud, Michael B. Sullivan, 2018, SC18: International Conference for High Performance Computing, Networking, Storage and Analysis.

SASSIFI : Evaluating Resilience of GPU Applications

Joel Emer, Timothy Tsai, Siva Hari, 2015 .

Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems

William J. Dally, Aditya Agrawal, Stephen W. Keckler, 2017, 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

A comparative analysis of microarchitecture effects on CPU and GPU memory system behavior

David A. Wood, Stephen W. Keckler, Joel Hestness, 2014, 2014 IEEE International Symposium on Workload Characterization (IISWC).

Counting Dependence Predictors

Franziska Roesner, Doug Burger, Stephen W. Keckler, 2008, 2008 International Symposium on Computer Architecture.

Scalable selective re-execution for EDGE architectures

Simha Sethumadhavan, Doug Burger, Stephen W. Keckler, 2004, ASPLOS XI.

Scalable hardware memory disambiguation for high-ILP processors

Simha Sethumadhavan, Doug Burger, Stephen W. Keckler, 2003, IEEE Micro.

Selective Re-Execution and its Implications for Value Speculation

Simha Sethumadhavan, Doug Burger, Stephen W. Keckler, 2022 .

Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications

Rangharajan Venkatesan, S. Keckler, Jason Clemons, 2022, ArXiv.

Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures

Krste Asanovic, Stephen W. Keckler, Ronny Krashinsky, 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

Thermal response to DVFS: analysis with an Intel Pentium M

Karthick Rajamani, Soraya Ghiasi, Freeman L. Rawson, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Implicit Memory Tagging: No-Overhead Memory Safety Using Alias-Free Tagged ECC

Michael B. Sullivan, S. Keckler, A. Jaleel, 2023, ISCA.

HarDNN: Fine-Grained Vulnerability Evaluation and Protection for Convolutional Neural Networks

Christopher W. Fletcher, Naresh R Shanbhag, Michael B. Sullivan, 2020 .

Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems

O. Mutlu, Kevin Hsieh, N. Vijaykumar, 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

Concurrent Event Handling through Multithreading

William J. Dally, Stephen W. Keckler, Sandeep Chatterjee, 1999, IEEE Trans. Computers.

Power, Performance, and Thermal Management for High-Performance Systems

Karthick Rajamani, Soraya Ghiasi, Freeman L. Rawson, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

Simha Sethumadhavan, Karthikeyan Sankaralingam, Doug Burger, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Implementation and Evaluation of On-Chip Network Architectures

Doug Burger, Stephen W. Keckler, Paul Gratz, 2006, 2006 International Conference on Computer Design.

Convergence and scalarization for data-parallel architectures

Krste Asanovic, Stephen W. Keckler, Ronny Krashinsky, 2013, Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO).

Selective GPU caches to eliminate CPU-GPU HW cache coherence

Thomas F. Wenisch, David W. Nellans, Stephen W. Keckler, 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection

Stephen W. Keckler, Brian Zimmer, Michael B. Sullivan, 2018, 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

A case for toggle-aware compression for GPU systems

Onur Mutlu, Todd C. Mowry, Gennady Pekhimenko, 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

Doug Burger, Stephen W. Keckler, Changkyu Kim, 2002, ASPLOS X.

Realistic Workload Characterization and Analysis for Networks-on-Chip Design

Stephen W. Keckler, Paul V. Gratz, S. Keckler, 2009 .

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology

William J. Dally, Yanqing Zhang, Brucek Khailany, 2019, 2019 IEEE Hot Chips 31 Symposium (HCS).

Measuring the Radiation Reliability of SRAM Structures in GPUs Designed for HPC

Luigi Carro, Stephen W. Keckler, Paolo Rech, 2014 .

Preemptive Virtual Clock: A flexible, efficient, and cost-effective QOS scheme for networks-on-chip

Onur Mutlu, Stephen W. Keckler, Boris Grot, 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Exploiting fine-grain thread level parallelism on the MIT multi-ALU processor

William J. Dally, Stephen W. Keckler, Daniel Maskit, 1998, Proceedings. 25th Annual International Symposium on Computer Architecture (Cat. No.98CB36235).

Chapter 2 On-Chip Networks for Multicore Systems

Sriram R. Vangal, Li-Shiuan Peh, Stephen W. Keckler, 2017 .

On-Chip Networks for Multicore Systems

Li-Shiuan Peh, Sriram Vangal, Stephen W. Keckler, 2009, Multicore Processors and Systems.

Exposing Memory Access Patterns to Improve Instruction and Memory Efficiency in GPUs

Stephen W. Keckler, Mark Stephenson, Neal C. Crago, 2018, ACM Trans. Archit. Code Optim..

Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches

Changkyu Kim, Stephen W. Keckler, Doug Burger, 2003, IEEE Micro.

Scaling to the end of silicon with EDGE architectures

Lizy Kurian John, Michael Dahlin, Kathryn S. McKinley, 2004, Computer.

Coordinated Power , Energy , and Temperature Management for High-Performance Microprocessors

Doug Burger, Stephen W. Keckler, Heather Hanson, 2004 .

Evaluation and optimization of multicore performance bottlenecks in supercomputing applications

James C. Browne, Martin Burtscher, Byoung-Do Kim, 2011, (IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE.

Making Sense of Performance Counter Measurements on Supercomputing Applications

James C. Browne, Martin Burtscher, Byoung-Do Kim, 2010 .

Retrospective: Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture

S. Keckler, K. Sankaralingam, D. Burger, 2023 .

A NUCA Substrate for Flexible CMP Cache Sharing

Jaehyuk Huh, Lixin Zhang, Doug Burger, 2007, IEEE Transactions on Parallel and Distributed Systems.

A NUCA substrate for flexible CMP cache sharing

Jaehyuk Huh, Lixin Zhang, Doug Burger, 2005, ICS.

On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories

Doug Burger, Stephen W. Keckler, Rajagopalan Desikan, 2004 .

Fast thread communication and synchronization mechanisms for a scalable single chip multiprocessor

Stephen W. Keckler, S. Keckler, 1998 .

Sharing Speculation : A Mechanism for Low-Latency Access to Falsely Shared Data

S. Keckler, D. Burger, Jaehyuk Huh, 2003 .

Exploring the design space of future CMPs

Jaehyuk Huh, Doug Burger, Stephen W. Keckler, 2001, Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques.

Recent extensions to the SimpleScalar tool suite

Todd M. Austin, Doug Burger, Stephen W. Keckler, 2004, PERV.

Community-based Matrix Reordering for Sparse Linear Algebra Optimization

S. Keckler, A. Jaleel, N. Crago, 2023, 2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Scalable On-Chip Interconnect Topologies

Stephen W. Keckler, Boris Grot, S. Keckler, 2008 .

Analysis of the TRIPS prototype block predictor

Doug Burger, Stephen W. Keckler, Nitya Ranganathan, 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

Combining Hyperblocks and Exit Prediction to Increase Front-End Bandwidth and Performance

Calvin Lin, Doug Burger, Stephen W. Keckler, 2002 .

Suraksha: A Framework to Analyze the Safety Implications of Perception Design Choices in AVs

Michael B. Sullivan, S. Keckler, Jishen Zhao, 2021, 2021 IEEE 32nd International Symposium on Software Reliability Engineering (ISSRE).

Vision Transformer Computation and Resilience for Dynamic Inference

Rangharajan Venkatesan, S. Keckler, Jason Clemons, 2022, 2212.02687.

Augmenting Legacy Networks for Flexible Inference

S. Keckler, Jason Clemons, J. Álvarez, 2023, 2023 IEEE Intelligent Vehicles Symposium (IV).

Stitch-X: An Accelerator Architecture for Exploiting Unstructured Sparsity in Deep Neural Networks

A. Parashar, S. Keckler, Y. Shao, 2018 .

Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing

J. Emer, S. Keckler, Jason Clemons, 2023, ACM Trans. Comput. Syst..

Estimating Silent Data Corruption Rates Using a Two-Level Model pdf

Joel Emer, Stephen W. Keckler, Paolo Rech, 2020, ArXiv.

An Analytical Model for Hardened Latch Selection and Exploration

Stephen W. Keckler, Brian Zimmer, Timothy Tsai, 2016 .

Exploiting Slack for Low Overhead Soft Error Reliability

Stephen W. Keckler, Premkishore Shivakumar, S. Keckler, 2007 .