Y. Yanagawa

In-substrate-bitline sense amplifier with array-noise-gating scheme for low-noise 4F2 DRAM array operable at 10-fF cell capacitance

Y. Yanagawa, T. Sekiguchi, A. Kotabe, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Asymmetric cross-coupled sense amplifier for small-sized 0.5-V gigabit-DRAM arrays

Y. Yanagawa, T. Sekiguchi, A. Kotabe, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

Solid-state Nanopore DNA Sequencing: Single-nucleotide Discrimination and Bidirectional DNA Translocation

Kenichi Takeda, Yoshimitsu Yanagawa, Rena Akahori, 2017 .

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing

Tomonori Sekiguchi, Yoshimitsu Yanagawa, Kazuo Ono, 2011, IEEE Journal of Solid-State Circuits.

Static charge outside chamber induces dielectric breakdown of solid-state nanopore membranes

Y. Yanagawa, K. Takeda, Yu Ishige, 2016 .