S. Narasimha

发表

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

S. Narasimha, K. Onishi, H. Nayfeh, 2006, 2006 International Electron Devices Meeting.

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

S. Narasimha, K. Onishi, J. Johnson, 2012, 2012 International Electron Devices Meeting.

Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

S. Narasimha, A. Waite, J. Johnson, 2007, 2007 IEEE Symposium on VLSI Technology.

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM

G. Freeman, Shreesh Narasimha, James P. Norum, 2015, IBM J. Res. Dev..

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

S. Narasimha, M. Hargrove, R. Pal, 2011, 2011 International Electron Devices Meeting.

An integrated methodology for accurate extraction of S/D series resistance components in nanoscale MOSFETs

S. Narasimha, K. Rim, Seong-Dong Kim, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Thin silicon String Ribbon for high efficiency polycrystalline solar cells

Ajeet Rohatgi, R. L. Wallace, S. Narasimha, 1997, Conference Record of the Twenty Sixth IEEE Photovoltaic Specialists Conference - 1997.

Design, fabrication, and analysis of greater than 18% efficient multicrystalline silicon solar cells

S. Narasimha, A. Rohatgi, 1997 .

Effective passivation of the low resistivity silicon surface by a rapid thermal oxide/plasma silicon nitride stack

S. Narasimha, A. Rohatgi, 1998 .

Effective Passivation of the Low Resistivity Silicon Surface by a Rapid Thermal Oxide/PECVD Silicon Nitride Stack and Its Application to Passivated Rear and Bifacial Si Solar Cells

S. Narasimha, A. Rohatgi, D. Ruby, 1998 .

A 243-GHz F/sub t/ and 208-GHz F/sub max/, 90-nm SOI CMOS SoC technology with low-power mm-wave digital and RF circuit capability

R. Trzcinski, S. Narasimha, N. Zamdmer, 2005, IEEE Transactions on Electron Devices.

SOI CMOS SoC Technology With Low-Power mmWave Digital and RF Circuit Capability

Jean-Olivier Plouchart, Jonghae Kim, Lawrence F. Wagner, 2005 .

Fabrication and analysis of record high 18.2% efficient solar cells on multicrystalline silicon material

S. Narasimha, A. Rohatgi, S. Kamra, 1996, IEEE Electron Device Letters.

Application of an SOI

S. Narasimha, N. Lustig, S. Kosonocky, 2003 .

Segment removal strategy in SAQP for advanced BEOL application

Jason Eugene Stephens, S. Narasimha, T. Spooner, 2017, 2017 IEEE International Interconnect Technology Conference (IITC).

Planarity considerations in SADP for advanced BEOL patterning

Jason Eugene Stephens, E. T. Ryan, S. Narasimha, 2017, 2017 IEEE International Interconnect Technology Conference (IITC).

Simulation Study on Channel Length Scaling of High Performance Partially Depleted Metal Gate and Poly Gate SOI MOSFETs

S. Narasimha, R. Dennard, W. Haensch, 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

Gate-dielectric permitivity and metal-gate work-function tradeoff in L/sub met/=25nm PDSOI device characteristics

S. Narasimha, M. Khare, R. Miller, 2006, IEEE Electron Device Letters.

An optimized rapid aluminum back surface field technique for silicon solar cells

Ajeet Rohatgi, S. Narasimha, S. Narasimha, 1999 .

University Center of Excellence for Photovoltaics Research and Education: Annual report

Ajeet Rohatgi, S. Narasimha, G. Crotty, 1995 .

Back surface field effects in the 17.3% efficient n-type dendritic web silicon solar cells

S. Narasimha, A. Rohatgi, G. Crotty, 1998 .

Fabrication and characterization of 18.6% efficient multicrystalline silicon solar cells

S. Narasimha, A. Rohatgi, 1998 .

Back surface field and emitter passivation effects in the record high efficiency n-type dendritic web silicon solar cell

S. Narasimha, A. Rohatgi, G. Crotty, 1997, Conference Record of the Twenty Sixth IEEE Photovoltaic Specialists Conference - 1997.

Record high 18.6% efficient solar cell on HEM multicrystalline material

S. Narasimha, A. Rohatgi, P. Doshi, 1996, Conference Record of the Twenty Fifth IEEE Photovoltaic Specialists Conference - 1996.

Ti and NiPt/Ti liner silicide contacts for advanced technologies

F. Chafik, S. Jain, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

Challenges of nickel silicidation in CMOS technologies

S. Narasimha, K. Nummy, J. Jordan-Sweet, 2015 .

A high performance 0.13 /spl mu/m SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

G. Biery, S. Narasimha, J. Adkisson, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A 7nm CMOS technology platform for mobile and high performance compute application

J. Zeng, S. Samavedam, B. Senapati, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications

D. Daley, L. Wagner, S. Narasimha, 2012, 2012 Symposium on VLSI Technology (VLSIT).

New breakdown data generation and analytics methodology to address BEOL and mol dielectric TDDB process development and technology qualification challenges

Fen Chen, Kai Zhao, Cathryn Christiansen, 2014, 2014 IEEE International Reliability Physics Symposium.

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

G. Burbach, D. Greenlaw, S.F. Huang, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Understanding and implementation of rapid thermal technologies for high-efficiency silicon solar cells

Ajeet Rohatgi, S. Narasimha, Abasifreke Ebong, 1999 .

Rapid processing of low-cost, high-efficiency silicon solar cells

S. Narasimha, A. Rohatgi, A. Ebong, 1999 .

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

S. Narasimha, J. Johnson, M. Khare, 2015, Symposium on VLSI Technology.

Record RF performance of 45-nm SOI CMOS Technology

B. Jagannathan, Jonghae Kim, Sungjae Lee, 2007, 2007 IEEE International Electron Devices Meeting.

A 243-GHz F/sub t/ and 208-GHz F/sub max/, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability

Jonghae Kim, R. Trzcinski, S. Narasimha, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs

S. Narasimha, A. Mocuta, K. Rim, 2002, Digest. International Electron Devices Meeting,.