H. Nayfeh

发表

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

S. Narasimha, K. Onishi, H. Nayfeh, 2006, 2006 International Electron Devices Meeting.

Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage

H. Nayfeh, M. Ieong, J. Kedzierski, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Strained silicon MOSFET technology

H. Nayfeh, D. Antoniadis, E. Fitzgerald, 2002, Digest. International Electron Devices Meeting,.

1 Nanostructures Technology , Research and Applications

R. C. Fleming, J. M. Carter, H. Nayfeh, 2001 .

Infrared spectroscopy and secondary ion mass spectrometry of luminescent, nonluminescent, and metal quenched porous silicon

Hasan M. Nayfeh, H. Nayfeh, M. Nayfeh, 1994 .

Demonstration of quantum volume 64 on a superconducting quantum computing system

Markus Brink, Mary Beth Rothwell, Giacomo Nannicini, 2020, Quantum Science and Technology.

Correlation of silicon microroughness with electrical parameters of SOI-AS (silicon-on-insulator with active substrate)

Hasan M. Nayfeh, H. Nayfeh, 1998 .

A 7nm CMOS technology platform for mobile and high performance compute application

J. Zeng, S. Samavedam, B. Senapati, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs

H. Nayfeh, L. Black, M. Khare, 2006, IEEE Electron Device Letters.

Trade-Offs Between RF Performance and Total-Dose Tolerance in 45-nm RF-CMOS

En Xia Zhang, J. D. Cressler, R. D. Schrimpf, 2011, IEEE Transactions on Nuclear Science.

Demonstration of quantum volume 64 on a superconducting quantum computing system

H. Nayfeh, J. Gambetta, L. Bishop, 2020, Quantum Science and Technology.

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

H. Nayfeh, D. Antoniadis, J. Hoyt, 2004, IEEE Transactions on Electron Devices.

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

Electrical characteristics of graphene wrinkles extracted by conductive Atomic Force Microscopy and electrical measurements on kelvin structures

Adel B. Gougam, Helmy Ally, Irfan Saadat, 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).