J. Johnson

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

S. Narasimha, K. Onishi, H. Nayfeh, 2006, 2006 International Electron Devices Meeting.

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

S. Narasimha, K. Onishi, J. Johnson, 2012, 2012 International Electron Devices Meeting.

A Room Temperature 0.1 /spl mu/m CMOS on SOI

J. Warnock, S. Furkay, D. Moy, 1993, Symposium 1993 on VLSI Technology.

Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

S. Narasimha, A. Waite, J. Johnson, 2007, 2007 IEEE Symposium on VLSI Technology.

Lateral ion implant straggle and mask proximity effect

J. Johnson, D. Hoyniak, P. Cottrell, 2003 .

Modeling of Gate Leakage, Floating Body Effect, and History Effect in 32nm HKMG PD-SOI CMOS

Y. Deng, J. Johnson, S. Springer, 2010 .

Anomalous low temperature charge leakage mechanism in ULSI flash memories

J. Johnson, T. Chen, K. Kitamura, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications

D. Daley, L. Wagner, S. Narasimha, 2012, 2012 Symposium on VLSI Technology (VLSIT).

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

S. Narasimha, J. Johnson, M. Khare, 2015, Symposium on VLSI Technology.