I. Ahsan

发表

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

S. Narasimha, K. Onishi, H. Nayfeh, 2006, 2006 International Electron Devices Meeting.

HERMES Core – A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing

I. Ahsan, E. Eleftheriou, V. Narayanan, 2021, 2021 Symposium on VLSI Circuits.

Fully on-chip MAC at 14nm enabled by accurate row-wise programming of PCM-based weights and parallel vector-transport in duration-format

P. Narayanan, I. Ahsan, G. Burr, 2021, 2021 Symposium on VLSI Technology.

A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

Xavier Timoneda Comas, M. Rasch, I. Ahsan, 2022, Nature Electronics.

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

I. Ahsan, E. Eleftheriou, A. Sebastian, 2022, IEEE Journal of Solid-State Circuits.

A 7nm CMOS technology platform for mobile and high performance compute application

J. Zeng, S. Samavedam, B. Senapati, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

An analog-AI chip for energy-efficient speech recognition and transcription

P. Narayanan, I. Ahsan, G. Burr, 2023, Nature.

Challenges of accurate gate length characterization with emphasis on the effects of intra-die thermal variation

Ishtiaq Ahsan, I. Ahsan, 2008 .

Fully On-Chip MAC at 14 nm Enabled by Accurate Row-Wise Programming of PCM-Based Weights and Parallel Vector-Transport in Duration-Format

I. Ahsan, A. Friz, W. Haensch, 2021, IEEE Transactions on Electron Devices.