P. Fisher

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

S. Narasimha, K. Onishi, H. Nayfeh, 2006, 2006 International Electron Devices Meeting.

Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micro bulk MOSFET devices?

P. Fisher, J. Bokor, Shiying Xiong, 2004, IEEE Transactions on Semiconductor Manufacturing.

Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

S. Narasimha, A. Waite, J. Johnson, 2007, 2007 IEEE Symposium on VLSI Technology.

Gate line-edge roughness effects in 50-nm bulk MOSFET devices

Shiying Xiong, Jeffrey Bokor, Qi Xiang, 2002, SPIE Advanced Lithography.