C. Tian

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

S. Narasimha, K. Onishi, H. Nayfeh, 2006, 2006 International Electron Devices Meeting.

Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process

Y. Liu, T. Nigam, S. Uppal, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

New breakdown data generation and analytics methodology to address BEOL and mol dielectric TDDB process development and technology qualification challenges

Fen Chen, Kai Zhao, Cathryn Christiansen, 2014, 2014 IEEE International Reliability Physics Symposium.

High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology

J. Sudijono, H. Utomo, M. Ieong, 2007, 2007 IEEE Symposium on VLSI Technology.

Reliability Investigation of NiPtSi Electrical Fuse With Different Programming Mechanisms

C. Tian, C. Kothandaraman, J. Safran, 2007, IEEE Transactions on Device and Materials Reliability.

Reliability Qualification of CoSi2 Electrical Fuse for 90Nm Technology

S.S. Iyer, J. Safran, N. Robson, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

NFET effective work function improvement via stress memorization technique in replacement metal gate technology

Y. Liu, S. Jain, S. Samavedam, 2013, 2013 Symposium on VLSI Technology.