H. van Meer

发表

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

S. Narasimha, K. Onishi, H. Nayfeh, 2006, 2006 International Electron Devices Meeting.

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper

M. Belyansky, L. Black, J. Holt, 2006, 2009 Symposium on VLSI Technology.

Limitations of shift-and-ratio based L/sub eff/ extraction techniques for MOS transistors with halo or pocket implants

N. Collaert, M. Rosmeulen, K. De Meyer, 2000, IEEE Electron Device Letters.

Ion implant applications to enable advances in semiconductor technologies

H. van Meer, T. Henry, K. V. Rao, 2017, 2017 17th International Workshop on Junction Technology (IWJT).

Effect of Schottky barrier alteration on the low-frequency noise of InP-based HEMTs

H. van Meer, D. Schreurs, M. Valenza, 1998, IEEE Electron Device Letters.

An Application of the Linear Errors-in-Variables Model in Semiconductor Device Performance Assessment

Necip Doganaksoy, Hans van Meer, H. van Meer, 2015 .

The spacer/replacer concept: a viable route for sub-100 nm ultrathin-film fully-depleted SOI CMOS

H. van Meer, K. De Meyer, 2002, IEEE Electron Device Letters.

Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures

H. van Meer, J. Jordan-Sweet, W. Wang, 2017, 2017 Symposium on VLSI Technology.

Process and local layout effect interaction on a high performance planar 20nm CMOS

S. Samavedam, M. Sherony, X. Wu, 2013, 2013 Symposium on VLSI Technology.

High performance raised Gate/Source/Drain transistors for sub-0.15 um CMOS technologies

H. van Meer, R. Loo, M. Caymax, 1999, 29th European Solid-State Device Research Conference.