M. Khare

发表

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

S. Narasimha, K. Onishi, H. Nayfeh, 2006, 2006 International Electron Devices Meeting.

Scaling of 32nm low power SRAM with high-K metal gate

R. Wong, X. Chen, M. Khare, 2008, 2008 IEEE International Electron Devices Meeting.

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Syed Muhammad Zain Zafar, M. Hargrove, C. Ouyang, 2007, 2007 IEEE Symposium on VLSI Technology.

Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

S. Narasimha, A. Waite, J. Johnson, 2007, 2007 IEEE Symposium on VLSI Technology.

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

S. Narasimha, M. Hargrove, R. Pal, 2011, 2011 International Electron Devices Meeting.

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

T. Adam, T. Standaert, M. Khare, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

X. Chen, M. Khare, D. Tekleab, 2008, 2008 Symposium on VLSI Technology.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

D. Corliss, T. Standaert, R. Wong, 2017, 2017 Symposium on VLSI Technology.

Plasma charging damage in SOI technology

A. Chou, M. Khare, J. Gambino, 2001, 2001 6th International Symposium on Plasma- and Process-Induced Damage (IEEE Cat. No.01TH8538).

Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics

M. Khare, T. Ning, T. Hook, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Diffusion and Defect Structure in Nitrogen Implanted Silicon

A. Domenicucci, M. Khare, P. Ronsheim, 2001 .

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

D. Greenlaw, H.-J. Engelmann, N. Kepler, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

A 243-GHz F/sub t/ and 208-GHz F/sub max/, 90-nm SOI CMOS SoC technology with low-power mm-wave digital and RF circuit capability

R. Trzcinski, S. Narasimha, N. Zamdmer, 2005, IEEE Transactions on Electron Devices.

High performance 0.18 /spl mu/m SOI CMOS technology

M. Sherony, G. Biery, T.-C. Chen, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs

T. B. Hook, T. Yamashita, T. E. Standaert, 2013, 2013 IEEE International Electron Devices Meeting.

Channel doping impact on FinFETs for 22nm and beyond

P. Oldiges, T. B. Hook, T. Yamashita, 2012, 2012 Symposium on VLSI Technology (VLSIT).

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

M. Khare, S. Luning, O. Faynot, 2013, 2013 IEEE International Electron Devices Meeting.

SOI CMOS SoC Technology With Low-Power mmWave Digital and RF Circuit Capability

Jean-Olivier Plouchart, Jonghae Kim, Lawrence F. Wagner, 2005 .

Extendibility of NiPt silicide to the 22-nm node CMOS technology

Anna W. Topol, K. Ohuchi, V. Narayanan, 2008, Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08).

Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology

Woo-Hyeong Lee, S.K.H. Fung, P. Agnello, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

The Interaction Challenges with Novel Materials in Developing High‐Performance and Low‐Leakage High‐k/Metal Gate CMOS Transistors

M. Khare, E. Cartier, V. Narayanan, 2012 .

Reliability issues for silicon-on-insulator

M. Khare, D. Badami, T. Hook, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Implant approaches and challenges for 20nm node and beyond ETSOI devices

M. Khare, S. Luning, B. Haran, 2011, IEEE 2011 International SOI Conference.

Gate-dielectric permitivity and metal-gate work-function tradeoff in L/sub met/=25nm PDSOI device characteristics

S. Narasimha, M. Khare, R. Miller, 2006, IEEE Electron Device Letters.

A comparative study of fin-last and fin-first SOI FinFETs

Josephine B. Chang, M. Khare, W. Haensch, 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Polarity-dependent oxide breakdown of NFET devices for ultra-thin gate oxide

R. Bolam, M. Khare, J. Sune, 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

A high performance 0.13 /spl mu/m SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

G. Biery, S. Narasimha, J. Adkisson, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node

Anna W. Topol, M. Khare, C. Lavoie, 2007, 2007 IEEE International Electron Devices Meeting.

Highly robust ultra-thin gate dielectric for giga scale technology

T. P. Ma, M. Khare, M. Khare, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

P. Oldiges, C. Park, N. Loubet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond

Phil Oldiges, Wilfried Haensch, Andres Bryant, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Uniaxial strain relaxation on ultra-thin strained-Si directly on insulator (SSDOI) substrates

C. Sung, M. Khare, M. Ieong, 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

M. Vinet, L. Grenouillet, T. Nagumo, 2012, 2012 International Electron Devices Meeting.

Full metal gate with borderless contact for 14 nm and beyond

B. Haran, V. Narayanan, J. Bruley, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs

H. Nayfeh, L. Black, M. Khare, 2006, IEEE Electron Device Letters.

A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

S. Narasimha, J. Johnson, M. Khare, 2015, Symposium on VLSI Technology.

Impact of back bias on ultra-thin body and BOX (UTBB) devices

M. Vinet, T. Skotnicki, L. Grenouillet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications

M. Khare, B. Haran, N. Loubet, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Performance and hot-carrier reliability of 100 nm channel length jet vapor deposited Si/sub 3/N/sub 4/ MNSFETs

Souvik Mahapatra, Juzer Vasi, Jason C. S. Woo, 2001 .

Dual layer SrTiO3/HfO2 gate dielectric for aggressively scaled band-edge nMOS devices

M. Khare, E. Cartier, V. Narayanan, 2007 .

Effects of water vapor anneal on MIS devices made of nitrided gate dielectrics

M. Khare, T. Ma, Xiewen Wang, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Jie Yang, Terence B. Hook, Andreas Knorr, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric

M. Khare, J. Woo, S. Mahapatra, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Transconductance in nitride-gate or oxynitride-gate transistors

M. Khare, M. Khare, T. Ma, 1999, IEEE Electron Device Letters.

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

A 243-GHz F/sub t/ and 208-GHz F/sub max/, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability

Jonghae Kim, R. Trzcinski, S. Narasimha, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..