P. Agnello

发表

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

S. Narasimha, K. Onishi, H. Nayfeh, 2006, 2006 International Electron Devices Meeting.

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

S. Narasimha, K. Onishi, J. Johnson, 2012, 2012 International Electron Devices Meeting.

Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

S. Narasimha, A. Waite, J. Johnson, 2007, 2007 IEEE Symposium on VLSI Technology.

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM

G. Freeman, Shreesh Narasimha, James P. Norum, 2015, IBM J. Res. Dev..

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

S. Narasimha, M. Hargrove, R. Pal, 2011, 2011 International Electron Devices Meeting.

An experimental and theoretical study of growth in horizontal epitaxial reactors

P. Agnello, S. Ghandhi, P. Chinoy, 1988 .

Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology

Woo-Hyeong Lee, S.K.H. Fung, P. Agnello, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Silicon epitaxy from silane by atmospheric‐pressure chemical vapor deposition at low temperatures

P. Agnello, T. Sedgwick, T. Kuan, 1992 .

High phosphorus doping of epitaxial silicon at low temperature and atmospheric pressure

P. Agnello, G. Scilla, T. Sedgwick, 1991 .

A 0.18 /spl mu/m high-performance logic technology

S. Greco, M. Hargrove, X. Chen, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Alkyl exchange effects between triethylindium and trimethylgallium

P. Agnello, S. Ghandhi, 1989 .

In-situ etching of InP by a low pressure transient HCI process

P. Agnello, S. Ghandhi, 1985 .

Conditions for an Oxide‐Free Si Surface for Low‐Temperature Processing: Steady‐State Boundary

P. Agnello, T. Sedgwick, 1992 .

Inhibition of Silicon Oxidation during Low Temperature Epitaxial Growth

P. Agnello, T. Sedgwick, 1992 .

Growth of Facet‐Free Selective Silicon Epitaxy at Low Temperature and Atmospheric Pressure

Tung-Sheng Kuan, P. D. Agnello, P. Agnello, 1991 .

The Use of Gas Monitors to Characterize a Low‐Temperature Atmospheric‐Pressure Epitaxial System

P. Agnello, T. Sedgwick, 1991 .

Silicides and local interconnections for high-performance VLSI applications

Paul D. Agnello, Randy W. Mann, Larry A. Clevenger, 1995, IBM J. Res. Dev..

Titanium silicide/germanide formation on submicron features for high mobility SiGe channel field effect transistors

P. Agnello, J. Ott, M. Tejwani, 1994 .

Improved control of momentary rapid thermal annnealing for silicidation

P. Agnello, A. Fink, 1993 .

A Mass Spectrometric Study of the Reaction of Triethylindium with Arsine Gas

P. Agnello, S. Ghandhi, 1988 .

Heavy arsenic doping of silicon grown by atmospheric‐pressure chemical vapor deposition at low temperatures

P. Agnello, J. Cotte, M. Goorsky, 1992 .

Atmospheric pressure chemical vapor deposition of Si and SiGe at low temperatures

P. Agnello, T. Sedgwick, 1992 .

A study of indium depletion in the OMVPE growth of GaInAs

P. Agnello, S. Ghandhi, P. Chinoy, 1990 .

The composition dependence of GaInAs grown by organometallic epitaxy

P. Agnello, S. Ghandhi, 1989 .

The Effect of Indium Depletion on the Composition of OMVPE Grown GaInAs

P. Agnello, S. Ghandhi, P. Chinoy, 1989 .

A high performance 0.13 /spl mu/m SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

G. Biery, S. Narasimha, J. Adkisson, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Process requirements for continued scaling of CMOS-the need and prospects for atomic-level manipulation

Paul D. Agnello, P. Agnello, 2002, IBM J. Res. Dev..

Effects of trace surface oxidation in low temperature epitaxy grown from dichlorosilane

P. Agnello, D. Grützmacher, T. Sedgwick, 1993 .

Selective growth of silicon‐germanium alloys by atmospheric‐pressure chemical vapor deposition at low temperatures

P. Agnello, J. Ott, G. Scilla, 1991 .

A 7nm CMOS technology platform for mobile and high performance compute application

J. Zeng, S. Samavedam, B. Senapati, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A high-performance 0.08 /spl mu/m CMOS

E. Nowak, A. Ray, P. Agnello, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Experimental 0.1 mu m p-channel MOSFET with p/sup +/-polysilicon gate on 35 AA gate oxide

Y. Taur, T. Lii, D. Quinlan, 1993, IEEE Electron Device Letters.

A High Performance 0.25/spl mu/m CMOS

J. Warnock, K. Jenkins, D. Klaus, 1993, Symposium 1993 on VLSI Technology.

CMOS active pixel image sensors fabricated using a 1.8 V, 0.25 /spl mu/m CMOS technology

P. Agnello, E. Crabbe, R.T. Chang, 1996, International Electron Devices Meeting. Technical Digest.

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

G. Burbach, D. Greenlaw, S.F. Huang, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond

Bernhard Wunder, Balaji Jayaraman, Subramanian S. Iyer, 2012, 2012 IEEE International Conference on IC Design & Technology.

The reactions of triethylindium and trimethylgallium with arsine gas

P. Agnello, S. Ghandhi, 1988 .

Growth rate enhancement of heavy n- and p-type doped silicon deposited by atmospheric-pressure chemical vapor deposition at low temperatures

P. D. Agnello, P. Agnello, J. Cotte, 1993 .