J. Cong

发表

Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks

Jason Cong, Zhenman Fang, Peipei Zhou, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Interconnect design for deep submicron ICs

J. Cong, Kei-Yong Khoo, Z. Pan, 1997, ICCAD 1997.

Simultaneous placement with clustering and duplication

J. Cong, Gang Chen, 2004 .

Technology mapping for FPGAs with embedded memory blocks

Jason Cong, Songjie Xu, J. Cong, 1998, FPGA '98.

Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping

Jason Cong, Yean-Yow Hwang, J. Cong, 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

A General Model for Fault Covering Problems in Reconfigurable Arrays

J. Cong, C. Liu, N. Hasan, 1989 .

Multilevel generalized force-directed method for circuit placement

Jason Cong, Tony F. Chan, Kenton Sze, 2005, ISPD '05.

Optimality and scalability study of existing placement algorithms

J. Cong, Chin-Chih Chang, M. Xie, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

Multi-level placement for large-scale mixed-size IC designs

J. Cong, Chin-Chih Chang, Xin Yuan, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

The survivability of design-specific spare placement in FPGA architectures with high defect rates

Jason Cong, Amit Agarwal, Brian Tagiku, 2013, TODE.

Fault covering problems in reconfigurable VLSI systems

P. McKinley, J. Cong, C. Liu, 1992 .

Bounded-skew clock and Steiner routing

Jason Cong, Cheng-Kok Koh, Andrew B. Kahng, 1998, TODE.

Bounded-skew clock and Steiner routing under Elmore delay

A. Kahng, J. Cong, Cheng-Kok Koh, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Optimal wiresizing under the distributed Elmore delay model

Jason Cong, Kwok-Shing Leung, J. Cong, 1993, ICCAD '93.

An interconnect-centric design flow for nanometer technologies

Jason Cong, J. Cong, 2001, Proc. IEEE.

Optimal wiresizing for interconnects with multiple sources

J. Cong, Lei He, Lei He, 1996, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Multiway partitioning with pairwise movement

J. Cong, S. Lim, 1998, ICCAD '98.

Interconnect layout optimization under higher-order RLC model

J. Cong, Cheng-Kok Koh, 1997, ICCAD 1997.

Optimal wiresizing under the distributed Elmore delay model

J. Cong, K. Leung, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Performance driven routing with multiple sources

Jason Cong, Patrick H. Madden, J. Cong, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

FPGA-based accelerator for long short-term memory recurrent neural networks

Jason Cong, Guangyu Sun, Yijin Guan, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Provably good algorithms for performance-driven global routing

J. Cong, G. Robins, M. Sarrafzadeh, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

Buffer block planning for interconnect-driven floorplanning

Jason Cong, David Z. Pan, Tianming Kong, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases

Tao Zhang, Jason Cong, Yiran Chen, 2018, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms

Jason Cong, Muhuan Huang, Yi Zou, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

AXR-CMP : Architecture Support in Accelerator-Rich CMPs

Jason Cong, Glenn Reinman, Chunyue Liu, 2011 .

Modeling and Mapping for Customizable Domain-Specific Computing

Vivek Sarkar, J. Cong, G. Reinman, 2010 .

High-performance clock routing based on recursive geometric matching

Jason Cong, Andrew B. Kahng, Gabriel Robins, 1991, 28th ACM/IEEE Design Automation Conference.

5 Conclusions and Directions for Future Work 4 Experimental Results

A. Kahng, J. Cong, 1998 .

On the Minimum Density Interconnection Tree Problem

Jason Cong, Majid Sarrafzadeh, Andrew B. Kahng, 1994 .

Matching-Based Methods for High-Performance

Jason Cong, Andrew B. Kahng, Gabriel Robins, 1993 .

ARA simulator PARADE [ ICCAD ' 15 ] is open source Accel TLB Shared TLB Accel TLB Accel TLB Accel

Cody Hao Yu, Zhenman Fang, J. Cong, 2018 .

System Synthesis and Automated Verification : Design Demands for IoT Devices

J. Cong, Deming Chen, W. Hwu, 2016 .

General convergent expectation maximization (EM)-type algorithms for image reconstruction

L. Vese, J. Cong, A. Bui, 2013 .

Fast floorplanning by look-ahead enabled recursive bipartitioning

J. Cong, M. Romesis, J.R. Shinned, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Low-power high-level synthesis for FPGA architectures

Deming Chen, Yiping Fan, J. Cong, 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

On the Construction of Optimal or Near-optimal Rectilinear Steiner Arborescence

J. Cong, K. Leung, 1994 .

A Communication-Centric Approach To Instruction Steering For Future Clustered Processors

Y. Tamir, J. Cong, G. Reinman, 2022 .

The Impact Of Compiler Optimizations On High-Level Synthesis

J. Cong, G. Reinman, T. Millstein, 2012 .

Routability-driven placement and white space allocation

J. Cong, Cheng-Kok Koh, P. Madden, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Bit-Level Transformation and Optimization for Hardware Synthesis of Algorithmic Descriptions

Mingxing Tan, J. Cong, Xu Cheng, 2009 .

Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion

Jason Cong, J. Cong, 1996 .

Fast Optimal Algorithms for the Minimum Rectilinear SteinerArborescence

J. Cong, 1997 .

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999

Jason Cong, David Blaauw, Farid N. Najm, 1999, International Symposium on Low Power Electronics and Design.

Intellectual property protection by watermarking combinational logic synthesis solutions

J. Cong, D. Kirovski, M. Potkonjak, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

Large-Scale Global Placement

Joseph R. Shinnerl, Jason Cong, J. Cong, 2007, Handbook of Approximation Algorithms and Metaheuristics.

Understanding Performance Gains of Accelerator-Rich Architectures ( Invited Paper )

Zhenman Fang, J. Cong, G. Reinman, 2019 .

Advanced Routing Techniques for Nanometer IC Designs

J. Cong, R. Rutenbar, T. Gao, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

CLinput Queue CLoutput Queue Compute DMALoad Load Queue DMAStore Store Queue ... Pack Send Queue Send Unpack Recv Queue Recv Input Java Objects Output Java Objects Pack Send Queue Send Unpack Recv Queue Recv

Cody Hao Yu, J. Cong, Peng Wei, 2018 .

Automated Generation of High-Performance Large-Scale Matrix Multiplication Accelerator on FPGA

J. Cong, Jie Wang, 2016 .

Client RM AM NM NM Container Container Job submission Note status Application status Resource request

Cody Hao Yu, Zhenman Fang, J. Cong, 2016 .

Re-form : FPGA-powered true codesign flow for high-performance computing in the post-Moore era

J. Cong, Kazutomo Yoshii, F. Cappello, 2016 .

CS-BWAMEM : A fast and scalable read aligner at the cloud scale for whole genome sequencing

P. Spellman, Peipei Zhou, J. Cong, 2015 .

The A 3 D Physical Design Flow Based on OpenAccess

J. Cong, Guojie Luo, 2022 .

Proceedings of the First International Workshop on Post Moore ' s Era Supercomputing

J. Cong, J. Shalf, Kazutomo Yoshii, 2016 .

Pilot – A Platform-Based HW / SW Synthesis System for FPSoC *

J. Cong, Zhiru Zhang, Yiping Fan, 2002 .

Interconnect design for deep submicron ICs

Jason Cong, Cheng-Kok Koh, Lei He, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Gradual relaxation techniques with applications to behavioral synthesis

J. Cong, M. Potkonjak, Zhiru Zhang, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Authors' Draft: Ieee Transactions on Computer-aided Design of Integrated Circuits and Systems, 2001 Pseudo Pin Assignment with Crosstalk Noise Control

J. Cong, 2001 .

Minimum Density Interconneciton Trees

Jason Cong, Majid Sarrafzadeh, Andrew B. Kahng, 1993, ISCAS.

Multi-way partitioning using bi-partition heuristics

Jason Cong, Majid Sarrafzadeh, Maogang Wang, 2000, ASP-DAC '00.

Serpens: a high bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplication

J. Cong, Yuze Chi, Linghao Song, 2021, DAC.

An enhanced multilevel algorithm for circuit placement

Joseph R. Shinnerl, Jason Cong, Tony F. Chan, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Large-scale circuit placement: gap and promise

J. Cong, M. Xie, Xin Yuan, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Further Studies on Placement Optimality

J. Cong, J. Shinnerl, Michalis Romesis, 2022 .

Enhanced robustness in multilevel mixed-size placement

Joseph R. Shinnerl, Jason Cong, Min Xie, 2005 .

Physical Synthesis for Power under Process Variation

J. Cong, 2006 .

Improving GNN-based accelerator design automation with meta learning

J. Cong, Yizhou Sun, Yunsheng Bai, 2022, DAC.

High-performance vlsi global routing

Jason Cong, Patrick H. Madden, J. Cong, 1998 .

Accel TLB Main Memory IOMMUMMU Core TLB MMU Core Accel Interconnect Scratchpad Accel Datapath

Zhenman Fang, J. Cong, Y. Hao, 2017 .

RASP : A Performance-Driven General Logic Synthesis System for SRAM-based FPGAs

Jason Cong, Songjie Xu, Yuzheng Ding, 1998 .

Simultaneous buffer and wire sizing for performance and power optimization

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

Optimal wiresizing for interconnects with multiple sources

J. Cong, Lei He, 1995, ICCAD 1995.

Domain-Specific Quantum Architecture Optimization

J. Cong, M. Niu, Wan-Hsuan Lin, 2022, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

OverGen: Improving FPGA Usability through Domain-specific Overlay Generation

J. Cong, Lu Zhang, Jian Weng, 2022, 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO).

Thermal-driven multilevel routing for 3-D ICs

Jason Cong, Yan Zhang, J. Cong, 2005, Asia and South Pacific Design Automation Conference.

FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-Level Synthesis

Adnan Darwiche, J. Cong, Yujia Shen, 2022, ACM Transactions on Reconfigurable Technology and Systems.

Thermal-driven multilevel routing for 3D ICs

Yan Zhang, J. Cong, J. Cong, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Three Dimensional Integrated Circuit Design

Jason Cong, Sachin S. Sapatnekar, Yuan Xie, 2010 .

Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication pdf

Jason Cong, Yuze Chi, Atefeh Sohrabizadeh, 2021, FPGA.

Host FPGA Disk Host Fetch Data FPGA Return Result Host O ffl oad Data FPGA Return Result FPGA

Peipei Zhou, J. Cong, Bojie Li, 2018 .

Wiresizing with Driver Sizing for Performance and Power Optimization

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung, 1994 .

Exploiting signal flow and logic dependency in standard cell placement

J. Cong, D. Xu, 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

Qubit Mapping for Reconfigurable Atom Arrays

J. Cong, M. Lukin, D. Bluvstein, 2022, Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design.

How will CAD handle billion-transistor systems? (panel)

Jason Cong, Kenneth L. Shepard, Robert C. Aitken, 1998, International Conference on Computer Aided Design.

Optimal Layout Synthesis for Quantum Computing

J. Cong, Bochen Tan, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

FPGA HLS Today: Successes, Challenges, and Opportunities

P. Pan, J. Cong, K. Vissers, 2022, ACM Trans. Reconfigurable Technol. Syst..

Understanding Performance Differences of FPGAs and GPUs

Jason Cong, Zhenman Fang, Jingxian Xu, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms

Jason Cong, Zhenman Fang, Mau-Chung Frank Chang, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers: Invited Paper

Jason Cong, Di Wu, Muhuan Huang, 2016, ISLPED.

Invited: Heterogeneous datacenters: Options and opportunities

Jason Cong, Cody Hao Yu, Di Wu, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only)

Jason Cong, Yunsong Li, Jie Lei, 2016, FPGA.

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Jason Cong, Zhiru Zhang, Bin Liu, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks

Jason Cong, Chen Zhang, Yijin Guan, 2015, FPGA.

Scaling Up Physical Design: Challenges and Opportunities

Jason Cong, Guojie Luo, Jiaxi Zhang, 2016, ISPD.

Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface

Jason Cong, Hao Wu, Mau-Chung Frank Chang, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

AIM: accelerating computational genomics through scalable and noninvasive accelerator-interposed memory

Jason Cong, Zhenman Fang, Glenn Reinman, 2017, MEMSYS.

An efficient and versatile scheduling algorithm based on SDC formulation

Jason Cong, Zhiru Zhang, J. Cong, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA

Jason Cong, Zhiru Zhang, Shih-Chieh Chang, 2008, 2008 Asia and South Pacific Design Automation Conference.

Optimality study of resource binding with multi-Vdds

Jason Cong, Deming Chen, Yiping Fan, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Wire width planning for interconnect performance optimization

Jason Cong, David Z. Pan, J. Cong, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Layout optimization

Jason Cong, Cheng-Kok Koh, Lei He, 1997 .

An efficient approach to simultaneous transistor and interconnect sizing

J. Cong, Lei He, 1996, Proceedings of International Conference on Computer Aided Design.

Optimal wiresizing under Elmore delay model

Jason Cong, Kwok-Shing Leung, J. Cong, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Performance-driven global routing for cell based ICs

Jason Cong, Chak-Kuen Wong, Majid Sarrafzadeh, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

On clock routing for general cell layouts

Jason Cong, Andrew B. Kahng, Gabriel Robins, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

Optimizing memory hierarchy allocation with loop transformations for high-level synthesis

Jason Cong, Peng Zhang, Yi Zou, 2012, DAC Design Automation Conference 2012.

Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs

Peng Zhang, Jason Cong, Cody Hao Yu, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Acceleration of EM-Based 3D CT Reconstruction Using FPGA

Jason Cong, Young Kyu Choi, J. Cong, 2016, IEEE Transactions on Biomedical Circuits and Systems.

High-performance CUDA kernel execution on FPGAs

Jason Cong, Deming Chen, Wen-mei W. Hwu, 2009, ICS.

Optimality Study of Existing Quantum Computing Layout Synthesis Tools pdf

Jason Cong, Bochen Tan, J. Cong, 2020, IEEE Transactions on Computers.

When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization pdf

Jason Cong, Jie Wang, Young-kyu Choi, 2020, ArXiv.

Optimal Qubit Mapping with Simultaneous Gate Absorption pdf

Jason Cong, Bochen Tan, J. Cong, 2021, ArXiv.

Scaling for edge inference of deep neural networks

J. Cong, Yiyu Shi, M. Niemier, 2018 .

PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators

J. Cong, Yuze Chi, Linghao Song, 2021, ICASSP 2022 - 2022 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

NSF Workshop on Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities

G. Cauwenberghs, J. Cong, P. Mazumder, 2021 .

PolySA: Polyhedral-Based Systolic Array Auto-Compilation

Jason Cong, Jie Wang, J. Cong, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks

Jason Cong, Zhenman Fang, Chen Zhang, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Minimizing Computation in Convolutional Neural Networks

Jason Cong, Bingjun Xiao, J. Cong, 2014, ICANN.

TGPA: Tile-Grained Pipeline Architecture for Low Latency CNN Inference

Peng Zhang, Jason Cong, Cody Hao Yu, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management

Jason Cong, Yun Liang, Xuechao Wei, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

INSIDER: Designing In-Storage Computing System for Emerging High-Performance Drive

Jason Cong, Tong He, Zhenyuan Ruan, 2019, USENIX Annual Technical Conference.

SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing

Jason Cong, Po-Tsang Huang, Tianhe Yu, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation

Jason Cong, Liancheng Jia, Jieming Yin, 2021, 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA).

AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA

Jason Cong, Licheng Guo, Jie Wang, 2021, FPGA.

Improving high level synthesis optimization opportunity through polyhedral transformations

Jason Cong, Peng Li, Yun Liang, 2013, FPGA '13.

An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

J. Cong, J. Cong, Y. Ding, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design

Jason Cong, M'Lissa Smith, J. Cong, 1993, 30th ACM/IEEE Design Automation Conference.

Impulse response analysis of coherent waveguide communication

Jason Cong, Adrian Tang, Tatsuo Itoh, 2017, International Journal of Microwave and Wireless Technologies.

Impulse response analysis of carrier-modulated multiband RF-interconnect (MRFI)

Jason Cong, Mau-Chung Frank Chang, Tatsuo Itoh, 2017 .

A thermal-driven floorplanning algorithm for 3D ICs

Jason Cong, Yan Zhang, Jie Wei, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

IEEE Journal on Emerging and Selected Topics in Circuits and Systems information for authors

Jason Cong, Ronald Tetzlaff, Gert Cauwenberghs, 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Behavior-level observability don't-cares and application to low-power behavioral synthesis

Jason Cong, Zhiru Zhang, Bin Liu, 2009, ISLPED.

Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures

Jason Cong, Sachin S. Sapatnekar, Yuan Xie, 2009 .

Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned pdf

Jason Cong, Jie Wang, J. Cong, 2021, ArXiv.

Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster

Jason Cong, Di Wu, Guangyu Sun, 2016, ISLPED.

Polyhedral-based data reuse optimization for configurable computing

Jason Cong, Peng Zhang, P. Sadayappan, 2013, FPGA '13.

BLINK: bit-sparse LSTM inference kernel enabling efficient calcium trace extraction for neurofeedback devices

Jason Cong, Zhe Chen, Hugh T. Blair, 2020, ISLPED.

LANMC: LSTM-Assisted Non-Rigid Motion Correction on FPGA for Calcium Image Stabilization

Jason Cong, Zhe Chen, Hugh T. Blair, 2019, FPGA.

CLINK: Compact LSTM Inference Kernel for Energy Efficient Neurofeedback Devices

Jason Cong, Zhe Chen, Hugh T. Blair, 2018, ISLPED.

FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates

Xi Chen, Wei Zhang, Jason Cong, 2017, 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Compilation and architecture support for customized vector instruction extension

Jason Cong, Bin Liu, Glenn Reinman, 2012, 17th Asia and South Pacific Design Automation Conference.

ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation

J. Cong, Yizhou Sun, Ziniu Hu, 2023, 2305.10838.

SACNN: Self-Attention Convolutional Neural Network for Low-Dose CT Denoising With Self-Supervised Perceptual Loss Network

Jason Cong, Wen Gao, Xiaodong Xie, 2020, IEEE Transactions on Medical Imaging.

An automated lung segmentation approach using bidirectional chain codes to improve nodule detection accuracy

Jason Cong, Alex A. T. Bui, William Hsu, 2015, Comput. Biol. Medicine.

Automated Accelerator Optimization Aided by Graph Neural Networks

J. Cong, Yizhou Sun, Yunsheng Bai, 2022, FPGA.

AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

Jason Cong, Cody Hao Yu, Atefeh Sohrabizadeh, 2020, ACM Trans. Design Autom. Electr. Syst..

HBM Connect: High-Performance HLS Interconnect for FPGA HBM

Jason Cong, Young-kyu Choi, Yuze Chi, 2021, FPGA.

Best-Effort FPGA Programming: A Few Steps Can Go a Long Way pdf

Cody Hao Yu, Chen Zhang, Zhenman Fang, 2018, ArXiv.

Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture pdf

Peng Zhang, Jason Cong, Peng Wei, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

FPGA Design Automation: A Survey

Jason Cong, Deming Chen, Peichen Pan, 2006, Found. Trends Electron. Des. Autom..

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers

Jason Cong, Peng Li, Peng Zhang, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

Jason Cong, Bingjun Xiao, J. Cong, 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

An efficient approach to multilayer layer assignment with anapplication to via minimization

Jason Cong, Chin-Chih Chang, J. Cong, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Performance optimization of VLSI interconnect layout

Jason Cong, Cheng-Kok Koh, Lei He, 1996, Integr..

A metric for layout-friendly microarchitecture optimization in high-level synthesis

Jason Cong, Bin Liu, J. Cong, 2012, DAC Design Automation Conference 2012.

Towards layout-friendly high-level synthesis

Jason Cong, Bin Liu, Guojie Luo, 2012, ISPD '12.

Cut ranking and pruning: enabling a general and efficient FPGA mapping solution

Jason Cong, Chang Wu, Yuzheng Ding, 1999, FPGA '99.

End-to-End Optimization of Deep Learning Applications

Jason Cong, Jie Wang, Atefeh Sohrabizadeh, 2020, FPGA.

AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

Cody Hao Yu, J. Cong, Atefeh Sohrabizadeh, 2022, ACM Trans. Design Autom. Electr. Syst..

SODA: Stencil with Optimized Dataflow Architecture

Jason Cong, Peng Wei, Peipei Zhou, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU

Jason Cong, Peng Wei, Zhenyuan Ruan, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration

Jason Cong, Zhenman Fang, Peng Wei, 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

A Novel High-Throughput Acceleration Engine for Read Alignment

Jason Cong, Peng Wei, Jie Lei, 2015, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines.

CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture

Peipei Zhou, J. Cong, Deming Chen, 2023, FPGA.

RapidStream: Parallel Physical Implementation of FPGA HLS Designs

J. Cong, Yuze Chi, Zhiru Zhang, 2022, FPGA.

AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs

Jason Cong, Yuze Chi, Ecenur Ustun, 2021, FPGA.

Extending High-Level Synthesis for Task-Parallel Programs

Jason Cong, Young-kyu Choi, Yuze Chi, 2020, 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Exploiting Computation Reuse for Stencil Accelerators

Jason Cong, Yuze Chi, J. Cong, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

HLScope+,: Fast and accurate performance estimation for FPGA HLS

Peng Zhang, Jason Cong, Peng Li, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A quantitative analysis on microarchitectures of modern CPU-FPGA platforms

Jason Cong, Zhenman Fang, Yuchen Hao, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators

Jason Cong, Peng Wei, Cody Hao Yu, 2021, FPGA.

Latte: Locality Aware Transformation for High-Level Synthesis

Jason Cong, Peng Wei, Cody Hao Yu, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication

Jason Cong, Zhenman Fang, Peipei Zhou, 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

A Fully Pipelined and Dynamically Composable Architecture of CGRA

Jason Cong, Peipei Zhou, Hui Huang, 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

CHARM: a composable heterogeneous accelerator-rich microprocessor

Jason Cong, Glenn Reinman, Michael Gill, 2012, ISLPED '12.

Multilevel Granularity Parallelism Synthesis on FPGAs

Jason Cong, Yun Liang, Deming Chen, 2011, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines.

FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs

Jason Cong, Deming Chen, Alexandros Papakonstantinou, 2009, 2009 IEEE 7th Symposium on Application Specific Processors.

Supporting Address Translation for Accelerator-Centric Architectures

Jason Cong, Yuchen Hao, Glenn Reinman, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs

Jason Cong, Yean-Yow Hwang, J. Cong, 2000, TODE.

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design

J. Cong, Yean-Yow Hwang, J. Cong, 1996, 33rd Design Automation Conference Proceedings, 1996.

Source-to-Source Optimization for HLS

Jason Cong, Peng Zhang, Yuxin Wang, 2016, FPGAs for Software Programmers.

Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities

W. Porod, G. Cauwenberghs, J. Cong, 2023, Proceedings of the IEEE.

Customizable Domain-Specific Computing

Jason Cong, Vivek Sarkar, Alex A. T. Bui, 2009, IEEE Design & Test of Computers.

Energy-efficient scheduling on heterogeneous multi-core architectures

Jason Cong, Bo Yuan, J. Cong, 2012, ISLPED '12.

Resource-Aware Throughput Optimization for High-Level Synthesis

Jason Cong, Peng Li, Peng Zhang, 2015, FPGA.

Mapping for better than worst-case delays in LUT-based FPGA designs

Jason Cong, Kirill Minkovich, J. Cong, 2008, FPGA '08.

Transformation from ad hoc EDA to algorithmic EDA

Jason Cong, J. Cong, 2012, ISPD '12.

Architecture and synthesis for multi-cycle communication

Jason Cong, Zhiru Zhang, Xun Yang, 2003, ISPD '03.

Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture

Wei Jiang, Yiping Fan, J. Cong, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Incremental physical design

Jason Cong, Majid Sarrafzadeh, J. Cong, 2000, ISPD '00.

Constrained floorplan design for flexible blocks

Jason Cong, C. L. Liu, Sai-keung Dong, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

An efficient design and implementation of LSM-tree based key-value store on open-channel SSD

Jason Cong, Guangyu Sun, Chen Zhang, 2014, EuroSys '14.

In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms

Jason Cong, Zhenman Fang, Yuchen Hao, 2019, ACM Trans. Reconfigurable Technol. Syst..

Design, Implementation, and Evaluation of "FRiTrace"

Fan Zhao, Shyhtsun Felix Wu, Wayne Huang, 2005, SEC.

A New Approach to Three- or

Jason Cong, C. L. Liu, D. F. Wong, 1988 .

Combined loop transformation and hierarchy allocation for data reuse optimization

Jason Cong, Peng Zhang, Yi Zou, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors

J. Cong, M. Lukin, D. Bluvstein, 2023, ArXiv.

A Study on the Impact of Compiler Optimizations on High-Level Synthesis

Jason Cong, Bin Liu, Peng Zhang, 2012, LCPC.

Optimal Qubit Mapping with Simultaneous Gate Absorption ICCAD Special Session Paper

J. Cong, Bochen Tan, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Assuring application-level correctness against soft errors

Jason Cong, Karthik Gururaj, J. Cong, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Optimal module and voltage assignment for low-power

Jason Cong, Deming Chen, Junjuan Xu, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Combining computation and communication optimizations in system synthesis for streaming applications

Jason Cong, Peng Zhang, Muhuan Huang, 2014, FPGA.

Combining module selection and replication for throughput-driven streaming programs

Jason Cong, Bin Liu, Muhuan Huang, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Simultaneous FU and Register Binding Based on Network Flow Method

Jason Cong, Junjuan Xu, J. Cong, 2008, 2008 Design, Automation and Test in Europe.

Low-power technology mapping for FPGA architectures with dual supply voltages

Jason Cong, Fei Li, Lei He, 2004, FPGA '04.

J. Cong, Deming Chen, 2004, Asia and South Pacific Design Automation Conference.

Architecture evaluation for power-efficient FPGAs

Jason Cong, Fei Li, Lei He, 2003, FPGA '03.

On the k-layer planar subset and topological via minimization problems

Jason Cong, C. L. Liu, J. Cong, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Power modeling and characteristics of field programmable gate arrays

Jason Cong, Fei Li, Lei He, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

Jason Cong, Fei Li, Yan Lin, 2004, FPGA '04.

Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture

Jason Cong, Yiping Fan, Junjuan Xu, 2009, TODE.

Revisiting FPGA Acceleration of Molecular Dynamics Simulation with Dynamic Data Flow Behavior in High-Level Synthesis pdf

Jason Cong, Zhenman Fang, Peng Wei, 2016, ArXiv.

LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization

Jason Cong, Deming Chen, Yiping Fan, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Optimal module and voltage assignment for low-power

Deming Chen, J. Cong, Junjuan Xu, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

S2FA: An Accelerator Automation Framework for Heterogeneous Computing in Datacenters

Jason Cong, Peng Wei, Cody Hao Yu, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

mPL6: enhanced multilevel mixed-size placement

Joseph R. Shinnerl, Jason Cong, Min Xie, 2006, ISPD '06.

An FPGA-Based BWT Accelerator for Bzip2 Data Compression

Jason Cong, Zhenman Fang, Mau-Chung Frank Chang, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Routability-driven placement and white space allocation

Jason Cong, Cheng-Kok Koh, Min Xie, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

An enhanced multilevel algorithm for circuit placement

T. Chan, J. Cong, K. Sze, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Optimality and scalability study of existing placement algorithms

Jason Cong, Min Xie, Chin-Chih Chang, 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Challenges and Opportunities for Design Innovations in Nanometer Technologies

Jason Cong, J. Cong, 1998 .

ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation

J. Cong, Yizhou Sun, Ziniu Hu, 2023, ArXiv.

Multilevel global placement with congestion control

Jason Cong, David Z. Pan, Xin Yuan, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Physical hierarchy generation with routing congestion control

Jason Cong, David Z. Pan, Chin-Chih Chang, 2002, ISPD '02.

Pseudopin assignment with crosstalk noise control

Jason Cong, Chin-Chih Chang, J. Cong, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Pseudo pin assignment with crosstalk noise control

Jason Cong, Chin-Chih Chang, J. Cong, 2000, ISPD '00.

On-chip interconnection network for accelerator-rich architectures

Jason Cong, Yuchen Hao, Glenn Reinman, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Accelerator-rich architectures: Opportunities and progresses

Jason Cong, Glenn Reinman, Karthik Gururaj, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Accelerator-rich CMPs: From concept to real hardware

Jason Cong, Muhuan Huang, Yu-Ting Chen, 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

xPilot: A Platform-Based Behavioral Synthesis System

Jason Cong, Zhiru Zhang, Deming Chen, 2005 .

Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale

Jason Cong, Zhenman Fang, Cody Hao Yu, 2016, SoCC.

RF-Interconnect for Future Network-On-Chip

Jason Cong, Mau-Chung Frank Chang, Eran Socher, 2011, Low Power Networks-on-Chip.

Power reduction of CMP communication networks via RF-interconnects

Jason Cong, Mau-Chung Frank Chang, Eran Socher, 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

BLINK

H. T. Blair, Garrett J. Blair, J. Cong, 2020, Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design.

Live Demonstration: Real-Time Calcium Trace Extraction from Large-Field-of-View Miniscope

Jason Cong, Hugh T. Blair, Daniel Aharoni, 2021, 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Optimal simultaneous mapping and clustering for FPGA delay optimization

Jason Cong, Deming Chen, Joey Y. Lin, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

NSF Workshop on EDA: Past, Present, and Future (Part 2)

Robert K. Brayton, Jason Cong, R. Brayton, 2010, IEEE Design & Test of Computers.

NSF Workshop on EDA: Past, Present, and Future (Part 1)

Robert K. Brayton, Jason Cong, R. Brayton, 2010, IEEE Des. Test Comput..

Robust gate sizing via mean excess delay minimization

Jason Cong, Lieven Vandenberghe, John Lee, 2008, ISPD '08.

Interconnect sizing and spacing with consideration of couplingcapacitance

Jason Cong, Cheng-Kok Koh, Lei He, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An integrated and automated memory optimization flow for FPGA behavioral synthesis

Jason Cong, Peng Zhang, Yuxin Wang, 2012, 17th Asia and South Pacific Design Automation Conference.

Platform characterization for Domain-Specific Computing

Jason Cong, Kwang-Ting Cheng, Alex A. T. Bui, 2012, 17th Asia and South Pacific Design Automation Conference.

Customizable Computing—From Single Chip to Datacenters

Jason Cong, Zhenman Fang, Peng Wei, 2019, Proceedings of the IEEE.

A Robust Mixed-Size Legalization and Detailed Placement Algorithm

Jason Cong, Min Xie, J. Cong, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multi-way VLSI Circuit Partitioning Based On Dual Net Representation

J. Cong, W. Lubio, N. Shivakumur, 1994, IEEE/ACM International Conference on Computer-Aided Design.

An Efficient Multilayer MCM Router Based on Four-Via Routing

Jason Cong, Kei-Yong Khoo, J. Cong, 1993, 30th ACM/IEEE Design Automation Conference.

On the k-layer planar subset and via minimization problems

Jason Cong, C. L. Liu, J. Cong, 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation pdf

Jason Cong, Yuze Chi, Atefeh Sohrabizadeh, 2021, FPGA.

Doppio: I/O-Aware Performance Analysis, Modeling and Optimization for In-memory Computing Framework

Jason Cong, Zhenman Fang, Peipei Zhou, 2018, 2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Atlas: Baidu's key-value storage system for cloud data

Jason Cong, Song Jiang, Guangyu Sun, 2015, 2015 31st Symposium on Mass Storage Systems and Technologies (MSST).

A Hybrid Architecture for Compressive Sensing 3-D CT Reconstruction

Jason Cong, Ming Yan, Jianwen Chen, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Net partitions yield better module partitions

Jason Cong, Andrew B. Kahng, Lars W. Hagen, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Via design rule consideration in multilayer maze routing algorithms

Jason Cong, Jie Fang, Kei-Yong Khoo, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections

Jason Cong, Peng Zhang, Yi Zou, 2012, J. Electr. Comput. Eng..

Efficient compilation of CUDA kernels for high-performance computing on FPGAs

Jason Cong, Deming Chen, Wen-mei W. Hwu, 2013, TECS.

FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects

Jason Cong, Bingjun Xiao, J. Cong, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Delay-optimal technology mapping for FPGAs with heterogeneous LUTs

Jason Cong, Songjie Xu, J. Cong, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Technology mapping and architecture evalution for k/m-macrocell-based FPGAs

Jason Cong, Xin Yuan, Hui Huang, 2005, TODE.

Minimum-cost bounded-skew clock routing

Jason Cong, Cheng-Kok Koh, J. Cong, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Global clustering-based performance-driven circuit partitioning

Jason Cong, Chang Wu, J. Cong, 2002, ISPD '02.

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Jason Cong, Peng Wei, Ramesh Karri, 2021, 2021 Formal Methods in Computer Aided Design (FMCAD).

Oscillatory neurocomputing with ring attractors: a network architecture for mapping locations in space onto patterns of neural synchrony

Jason Cong, Hugh T. Blair, Allan Wu, 2014, Philosophical Transactions of the Royal Society B: Biological Sciences.

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs

Jason Cong, Zhiru Zhang, Deming Chen, 2016, IET Cyper-Phys. Syst.: Theory & Appl..

Report for the NSF Workshop on Cross ‐ layer Power Optimization and Management

Jon C. Hiller, C. J. Holland, Benjamin C. Lee, 2012 .

Mapping a data-flow programming model onto heterogeneous platforms

Jason Cong, Vivek Sarkar, Yi Zou, 2012, LCTES '12.

Parallel multi-level analytical global placement on graphics processing units

Jason Cong, Yi Zou, J. Cong, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Performance driven multi-layer general area routing for PCB/MCM designs

Jason Cong, Patrick H. Madden, J. Cong, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

HLS-Based Optimization and Design Space Exploration for Applications with Variable Loop Bounds

Jason Cong, Young-kyu Choi, J. Cong, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Platform-Based Behavior-Level and System-Level Synthesis

Jason Cong, Zhiru Zhang, Wei Jiang, 2006, 2006 IEEE International SOC Conference.

A multilevel analytical placement for 3D ICs

Jason Cong, Guojie Luo, J. Cong, 2009, 2009 Asia and South Pacific Design Automation Conference.

An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness

Jason Cong, Yiyu Shi, Guojie Luo, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Architecture support for accelerator-rich CMPs

Jason Cong, Glenn Reinman, Michael Gill, 2012, DAC Design Automation Conference 2012.

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

Jason Cong, Cody Hao Yu, Zhe Chen, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing

Jason Cong, Cody Hao Yu, Yuan Zhou, 2019, FPGA.

Bandwidth optimization through on-chip memory restructuring for HLS

Jason Cong, Peng Wei, Cody Hao Yu, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Thermal-Aware 3D IC Placement Via Transformation

Jason Cong, Yan Zhang, Jie Wei, 2007, 2007 Asia and South Pacific Design Automation Conference.

Thermal-aware cell and through-silicon-via co-placement for 3D ICs

Jason Cong, Yiyu Shi, Guojie Luo, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

The DIMM tree architecture: A high bandwidth and scalable memory system

Jason Cong, Glenn Reinman, Kanit Therdsteerasukdi, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications

Jason Cong, Mau-Chung Frank Chang, Tatsuo Itoh, 2019, IEEE Journal of Solid-State Circuits.

Improved SAT-based Boolean matching using implicants for LUT-based FPGAs

Jason Cong, Kirill Minkovich, J. Cong, 2007, FPGA '07.

A scalable micro wireless interconnect structure for CMPs

Jason Cong, Songwu Lu, Lixia Zhang, 2009, MobiCom '09.

FPGA Simulation Engine for Customized Construction of Neural Microcircuit

Jason Cong, Hugh T. Blair, Di Wu, 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

Random walks for circuit clustering

Jason Cong, Andrew B. Kahng, L. Hagen, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration

Jason Cong, Yuze Chi, Jiajie Li, 2020, FPGA.

SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs

Jason Cong, Jie Wang, Yun Liang, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Coordinated resource optimization in behavioral synthesis

Jason Cong, Bin Liu, Junjuan Xu, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

Jason Cong, Zhiru Zhang, Deming Chen, 2007, 2007 Asia and South Pacific Design Automation Conference.

Optimal simultaneous module and multivoltage assignment for low power

Jason Cong, Deming Chen, Junjuan Xu, 2006, TODE.

Instruction set extension with shadow registers for configurable processors

Jason Cong, Zhiru Zhang, Glenn Reinman, 2005, FPGA '05.

Comparison Results on Fu and Register Counts Accurately Handle Don't-care Conditions in High-level Designs and Application for Reducing Initialized Registers Chou Et Al.: Accurately Handle Don't-care Conditions in High-level Designs and Application for Reducing Initialized Registers 647

R. Rivest, C. Leiserson, J. Cong, 2022 .

Lopass: a Low-power Architectural Synthesis System for Fpgas with Interconnect Estimation and Optimization Abstract—in This Paper, We Present a Low-power Architectural Synthesis System (lopass) for Field-programmable Gate-array (fpga) Designs with Interconnect Power Estimation and Opti- Mization. Lo

J. Cong, Deming Chen, Yiping Fan, 2022 .

High-Speed mm-Wave Data-Link Based on Hollow Plastic Cable and CMOS Transceiver

Jason Cong, Mau-Chung Frank Chang, Yanghyo Kim, 2013, IEEE Microwave and Wireless Components Letters.

A 125GHz transceiver in 65nm CMOS assembled with FR4 PCB antenna for contactless wave-connectors

Jason Cong, Mau-Chung Frank Chang, Yan Zhao, 2017, 2017 IEEE MTT-S International Microwave Symposium (IMS).

Energy efficient multiprocessor task scheduling under input-dependent variation

Jason Cong, Karthik Gururaj, J. Cong, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application

Faming Liang, Jason Cong, Wing Hung Wong, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Architecture and compilation for data bandwidth improvement in configurable embedded processors

Jason Cong, Zhiru Zhang, Guoling Han, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Nonconvex Optimization and Its Applications

Joseph R. Shinnerl, Jason Cong, Min Xie, 2013 .

Multilevel Circuit Placement

Joseph R. Shinnerl, Jason Cong, Tony F. Chan, 2003 .

Theory and algorithm for generalized memory partitioning in high-level synthesis

Jason Cong, Peng Li, Yuxin Wang, 2014, FPGA.

FLASH: Fast, Parallel, and Accurate Simulator for HLS

Jason Cong, Young-kyu Choi, Yuze Chi, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Throughput-oriented kernel porting onto FPGAs

Jason Cong, Yun Liang, Deming Chen, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Memory partitioning and scheduling co-optimization in behavioral synthesis

Jason Cong, Peng Li, Peng Zhang, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A reuse-aware prefetching scheme for scratchpad memory

Jason Cong, Yi Zou, Hui Huang, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Automatic memory partitioning and scheduling for throughput and power optimization

Jason Cong, Bin Liu, Wei Jiang, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

EM+TV for Reconstruction of Cone-beam CT with Curved Detectors using GPU

Jason Cong, Ming Yan, Alex A. T. Bui, 2011 .

for Delay Optimization

Jason Cong, Andrew B. Kahng, Los Angeles, 1992 .

A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications

Jason Cong, Adrian Tang, Mau-Chung Frank Chang, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Physical planning with retiming

Jason Cong, Sung Kyu Lim, J. Cong, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Provably good performance-driven global routing

Jason Cong, Chak-Kuen Wong, Majid Sarrafzadeh, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Application-specific instruction generation for configurable processor architectures

J. Cong, Zhiru Zhang, Yiping Fan, 2004, FPGA '04.

Simultaneous circuit partitioning/clustering with retiming for performance optimization

Honching Li, Chang Wu, J. Cong, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design

Jason Cong, Andrew B. Kahng, Kwok-Shing Leung, 1997, ISPD '97.

mPL6: a robust multilevel mixed-size placement engine

Joseph R. Shinnerl, Jason Cong, Min Xie, 2005, ISPD '05.

MARS-a multilevel full-chip gridless routing system

Jason Cong, Yan Zhang, Min Xie, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multilevel optimization for large-scale circuit placement

Joseph R. Shinnerl, Jason Cong, Tony F. Chan, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Modern Circuit Placement

Jason Cong, Gi-Joon Nam, J. Cong, 2008 .

Matching-based methods for high-performance clock routing

Jason Cong, Andrew B. Kahng, Gabriel Robins, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Large-Scale Global Placement

Jason Cong, Joseph R. Shinnerl, J. Cong, 2018, Handbook of Approximation Algorithms and Metaheuristics.

RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses

Jason Cong, Guangyu Sun, Nong Xiao, 2019, IEEE Transactions on Computers.

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998

Jason Cong, Sinan Kaptanoglu, J. Cong, 1998, FPGA.

Advanced Routing Techniques for Nanometer IC Designs

Rob A. Rutenbar, J. Cong, T. Gao, 2006, IEEE/ACM International Conference on Computer-Aided Design.

Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization

Jason Cong, Xin Yuan, David Z. Pan, 2001 .

Synthesis Algorithm for Application-Specific Homogeneous Processor Networks

Jason Cong, Wei Jiang, Guoling Han, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Synthesis of an application-specific soft multiprocessor system

Jason Cong, Wei Jiang, Guoling Han, 2007, FPGA '07.

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks

J. Cong, Guangyu Sun, Yijin Guan, 2015, FPGA.

VIA design rule consideration in multi-layer maze routing algorithms

Jason Cong, Jie Fang, Kei-Yong Khoo, 1999, ISPD '99.

Advances and Challenges in 3D Physical Design

Jason Cong, Guojie Luo, J. Cong, 2010, IPSJ Trans. Syst. LSI Des. Methodol..

Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors

J. Cong, M. Lukin, D. Bluvstein, 2023, ArXiv.

AutoPilot: A Platform-Based ESL Synthesis System

Jason Cong, Zhiru Zhang, Yiping Fan, 2008 .

Optimality Study of Logic Synthesis for LUT-Based FPGAs

Jason Cong, Kirill Minkovich, J. Cong, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Thee Supercomputerr Supernet: Aa Scalablee Distributedd Terabitt Network

L. Kleinrock, E. Gafni, J. Cong, 1995 .

Bounded-skew clock and Steiner routing under Elmore delay

A. Kahng, J. Cong, Cheng-Kok Koh, 1995, International Conference on Computer Aided Design.

Simultaneous buffer and wire sizing for performance and power optimization

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

Simultaneous Driver And Wire Sizing For Performance And Power Optimization*

Jason Cong, Cheng-Kok Koh, J. Cong, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Multiscale Optimization in VLSI Physical Design Automation

T. Chan, J. Cong, K. Sze, 2006 .

Large-scale circuit placement

Joseph R. Shinnerl, Jason Cong, Min Xie, 2005, TODE.

Optimality and stability study of timing-driven placement algorithms

Min Xie, J. Cong, M. Romesis, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Optimality, scalability and stability study of partitioning and placement algorithms

Jason Cong, Min Xie, Michail Romesis, 2003, ISPD '03.

An enhanced multilevel routing system

Jason Cong, Min Xie, Yan Zhang, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Multilevel approach to full-chip gridless routing

Jason Cong, Jie Fang, VI YanZhang, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Performance driven multi-level and multiway partitioning with retiming

Jason Cong, Sung Kyu Lim, Chang Wu, 2000, Proceedings 37th Design Automation Conference.

Routing tree construction under fixed buffer locations

Jason Cong, Xin Yuan, J. Cong, 2000, Proceedings 37th Design Automation Conference.

DUNE: a multi-layer gridless routing system with wire planning

Jason Cong, Jie Fang, Kei-Yong Khoo, 2000, ISPD '00.

Edge separability based circuit clustering with application to circuit partitioning

Jason Cong, Sung Kyu Lim, J. Cong, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

An implicit connection graph maze routing algorithm for ECO routing

Jason Cong, Jie Fang, Kei-Yong Khoo, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Multilevel Optimization in VLSICAD

Joseph R. Shinnerl, Jason Cong, J. Cong, 2003 .

Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design

A. Kahng, J. Cong, K. Leung, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Relaxed simulated tempering for VLSI floorplan designs

Faming Liang, Jason Cong, Wing Hung Wong, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Thermal-Aware 3D Floorplan

Jason Cong, Yuchun Ma, J. Cong, 2010 .

Scheduling with integer time budgeting for low-power optimization

Jason Cong, Miodrag Potkonjak, Zhiru Zhang, 2008, 2008 Asia and South Pacific Design Automation Conference.

A 3D physical design flow based on Open Access

Jason Cong, Guojie Luo, J. Cong, 2009, 2009 International Conference on Communications, Circuits and Systems.

3D Physical Design

Jason Cong, Guojie Luo, J. Cong, 2011 .

Improved crosstalk modeling for noise constrained interconnect optimization

P. V. Srinivas, J. Cong, D. Pan, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only)

Jason Cong, Bingjun Xiao, J. Cong, 2012, FPGA '12.

Pin assignment with global routing for general cell designs

Jason Cong, J. Cong, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Defect tolerance in nanodevice-based programmable interconnects: Utilization beyond avoidance

Jason Cong, Bingjun Xiao, J. Cong, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages

Jason Cong, Fei Li, Lei He, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Simultaneous Timing Driven Clustering and Placement for FPGAs

Jason Cong, Gang Chen, J. Cong, 2004, FPL.

Technology mapping for k/m-macrocell based FPGAs

Jason Cong, Xin Yuan, Hui Huang, 2000, FPGA '00.

A Go-to-FPGA Compilation Framework for Streaming Applications

J. Cong, Tianyi Cui, 2017 .

Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs

Jason Cong, Yuan Xie, Yijin Guan, 2020, IEEE Transactions on Computers.

An interconnect-centric design flow for nanometer technologies

Jason Cong, J. Cong, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

Large scale circuit partitioning with loose/stable net removal and signal flow based clustering

Jason Cong, Sung Kyu Lim, Toshiyuki Shibuya, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression

Jason Cong, Adrian Tang, Mau-Chung Frank Chang, 2012, 2012 IEEE International Solid-State Circuits Conference.

An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling

Jason Cong, Jongsun Kim, Mau-Chung Frank Chang, 2011, 2011 IEEE International Solid-State Circuits Conference.

Incremental CAD

Jason Cong, Olivier Coudert, Sharad Malik, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Edge separability-based circuit clustering with application to multilevel circuit partitioning

Jason Cong, Sung Kyu Lim, J. Cong, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Large Scale Circuit Partitioning With Loose/Stable Net Removal And Signal Flow Based Hierarchical Cl

Jason Cong, Sung Kyu Lim, Toshiyuki Shibuya, 1997, ICCAD 1997.

A scalable communication-aware compilation flow for programmable accelerators

Jason Cong, Hui Huang, Mohammad Ali Ghodrat, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Thermal-Aware 3D Placement

Jason Cong, Guojie Luo, J. Cong, 2010 .

The SMEM Seeding Acceleration for DNA Sequence Alignment

Jason Cong, Cody Hao Yu, Mau-Chung Frank Chang, 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).