E. Beyne

发表

Extreme wafer thinning optimization for via-last applications

Eric Beyne, Dave Thomas, Anne Jourdain, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

Characterization of Extreme Si Thinning Process for Wafer-to-Wafer Stacking

A. Jourdain, F. Inoue, E. Beyne, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

E. Beyne, H. Dekkers, E. Van Besien, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime

G. Beyer, E. Beyne, A. Thean, 2014, 2014 IEEE International Electron Devices Meeting.

Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology

G. Beyer, E. Beyne, A. Redolfi, 2013, 2013 IEEE International Electron Devices Meeting.

Correlation between Cu microstructure and TSV Cu pumping

E. Beyne, K. Croes, H. Philipsen, 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

Noise coupling between TSVs and active devices: Planar nMOSFETs vs. nFinFETs

E. Beyne, J. Raskin, V. Moroz, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

In-depth Raman spectroscopy analysis of various parameters affecting the mechanical stress near the surface and bulk of Cu-TSVs

E. Beyne, V. Simons, I. De Wolf, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Advanced metallization scheme for 3×50µm via middle TSV and beyond

G. Beyer, E. Beyne, S. Van Huylenbroeck, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Impact of post-plating anneal and through-silicon via dimensions on Cu pumping

E. Beyne, K. Croes, H. Philipsen, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

The 3-D Interconnect Technology Landscape

Eric Beyne, E. Beyne, 2016, IEEE Design & Test.

Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology

G. Beyer, E. Beyne, A. Thean, 2012, 2012 International Electron Devices Meeting.

Reliable Via-Middle Copper Through-Silicon Via Technology for 3-D Integration

E. Beyne, 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Small Pitch, High Aspect Ratio Via-Last TSV Module

G. Beyer, E. Beyne, S. Van Huylenbroeck, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

3D Integration Technologies at IMEC

E. Beyne, 2008 .

Numerical and experimental characterization of the thermal behavior of a packaged DRAM-on-logic stack

E. Beyne, P. Marchal, G. Van der Plas, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Cost comparison between 3D and 2.5D integration

Eric Beyne, Erik Jan Marinissen, Mikael Detalle, 2012, 2012 4th Electronic System-Integration Technology Conference.

Processing active devices on Si interposer and impact on cost

Eric Beyne, Erik Jan Marinissen, Mirko Scholz, 2015, 2015 International 3D Systems Integration Conference (3DIC).

Fat damascene wires for high bandwidth routing in silicon interposer

G. Beyer, E. Beyne, J. Ryckaert, 2012 .

A High-Bandwidth Fine-Pitch 2.57Tbps/mm In-package Communication Link Achieving 48fJ/bit/mm Efficiency

Eric Beyne, Dimitrios Velenis, Marian Verhelst, 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

A fully-packaged electromagnetic microrelay

E. Beyne, J. Bergqvist, H. Tilmans, 1999, Technical Digest. IEEE International MEMS 99 Conference. Twelfth IEEE International Conference on Micro Electro Mechanical Systems (Cat. No.99CH36291).

Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology

O. O. Okudur, Andy Miller, G. Beyer, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Interposer technology for high band width interconnect applications

G. Beyer, E. Beyne, J. de Vos, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

Through-silicon via and die stacking technologies for microsystems-integration

A. Jourdain, E. Beyne, B. Swinnen, 2008, 2008 IEEE International Electron Devices Meeting.

3D stacked IC demonstration using a through Silicon Via First approach

A. Jourdain, E. Beyne, B. Parvais, 2008, 2008 IEEE International Electron Devices Meeting.

Parylene N as a dielectric material for through silicon vias

E. Beyne, B. Majeed, D. Tezcan, 2008, 2008 58th Electronic Components and Technology Conference.

The indent reflow sealing (IRS) technique-a method for the fabrication of sealed cavities for MEMS devices

E. Beyne, H. Tilmans, D.J. van de Peer, 2000, Journal of Microelectromechanical Systems.

3D stacking using Cu-Cu direct bonding for 40um pitch and beyond

K. Rebibis, E. Beyne, A. L. Manna, 2012, 2012 4th Electronic System-Integration Technology Conference.

Conjugate Heat Transfer and Fluid Flow Modeling for Liquid Microjet Impingement Cooling with Alternating Feeding and Draining Channels

E. Beyne, M. Baelmans, V. Cherman, 2019, Fluids.

Transient thermal modeling and characterization of a hybrid component

E. Beyne, F. Christiaens, 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.

3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

E. Beyne, P. Jaenen, H. Philipsen, 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Temperature dependent electrical characteristics of through-si-via (TSV) interconnections

A. Jourdain, E. Beyne, A. Mercha, 2010, 2010 IEEE International Interconnect Technology Conference.

Polymer Filling of Silicon Trenches for 3-D Through Silicon vias Applications

E. Beyne, Y. Civale, P. Soussan, 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Effects of packaging on mechanical stress in 3D-ICs

G. Beyer, E. Beyne, J. de Vos, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

3D stacking induced mechanical stress effects

G. Beyer, E. Beyne, J. de Vos, 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias

E. Beyne, B. Swinnen, L. Bogaerts, 2006, 2006 International Electron Devices Meeting.

Surface Treatment to Enable Low Temperature and Pressure Copper Direct Bonding

K. Rebibis, E. Beyne, I. De Wolf, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications

A. Jourdain, E. Beyne, A. Redolfi, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Integration and manufacturing aspects of moving from WaferBOND HT-10.10 to ZoneBOND material in temporary wafer bonding and debonding for 3D applications

A. Jourdain, K. Rebibis, Andy Miller, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

Electrodeposition for the synthesis of microsystems

E. Beyne, J. Fransaer, P. Merken, 2000 .

3D Wafer Level Packaging Approach Towards Cost Effective Low Loss High Density 3D Stacking

E. Beyne, P. Pieters, 2006, 2006 7th International Conference on Electronic Packaging Technology.

Via-middle through-silicon via with integrated airgap to zero TSV-induced stress impact on device performance

G. Beyer, E. Beyne, A. Redolfi, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

Generalized analysis of coupled lines in multilayer microwave MCM-D technology-application: integrated coplanar Lange couplers

E. Beyne, R. Mertens, P. Pieters, 1999 .

Modeling of Buck Converter with 3D Air-Core Inductor

E. Beyne, R. Lauwereins, D. Velenis, 2020, 2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC).

3D Heterogeneous Package Integration of Air/Magnetic Core Inductor: 89%-Effi- ciency Buck Converter with Backside Power Delivery Network

Andy Miller, E. Beyne, C. Adelmann, 2020, 2020 IEEE Symposium on VLSI Technology.

Inductance and quality-factor evaluation of planar lumped inductors in a multilayer configuration

E. Beyne, S. Mahmoud, 1997 .

Integrated microwave filters in MCM-D

E. Beyne, P. Pieters, S. Brebels, 1996, Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893).

Direct Au and Cu wire bonding on Cu/low-k BEOL

C. J. Vath, E. Beyne, P. Banda, 2002, 4th Electronics Packaging Technology Conference, 2002..

Fine pitch copper wire bonding on copper bond pad process optimization

C. J. Vath, E. Beyne, M. Van De Peer, 2002, Proceedings of the 4th International Symposium on Electronic Materials and Packaging, 2002..

FEM study of deformation and stresses in copper wire bonds on Cu lowK structures during processing

E. Beyne, B. Vandevelde, D. Degryse, 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

Mechanical FEM Simulation of bonding process on Cu lowK wafers

E. Beyne, B. Vandevelde, D. Degryse, 2004, IEEE Transactions on Components and Packaging Technologies.

Compensating differences between measurement and calibration wafer in probe-tip calibrations

E. Beyne, W. De Raedt, G. Carchon, 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).

Evaluation of UBM oxidation through air exposure and heating and effectiveness of wet and plasma cleaning on solder joint formation during TCB

Andy Miller, G. Beyer, E. Beyne, 2020, 2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC).

Challenges and solutions on pre-assembly processes for thinned 3D wafers with micro-bumps on the backside

R. A. Miller, K. Rebibis, G. Beyer, 2014, 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).

Process development to enable 3D IC multi-tier die bond for 20μM pitch and beyond

Doug C. H. Yu, K. Rebibis, G. Beyer, 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

Degradation of Cu6Sn5 intermetallic compound by pore formation in solid-liquid interdiffusion Cu/Sn microbump interconnects

E. Beyne, K. Croes, K. Wolter, 2014 .

3D Stacking Using Bump-Less Process for Sub 10um Pitch Interconnects

A. Jourdain, F. Inoue, K. Rebibis, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Multilayer thin-film technology enabling technology for solving high-density interconnect and assembly problems

Eric Beyne, E. Beyne, 2003 .

Thermomechanical models for leadless solder interconnections in flip chip assemblies

Bart Vandevelde, Eric Beyne, Joris Peeters, 1998 .

Analysis of the Induced Stresses in Silicon During Thermcompression Cu-Cu Bonding of Cu-Through-Vias in 3D-SIC Architecture

E. Beyne, G. Eneman, S. Stoukatch, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

Cost effectiveness of 3D integration options

Eric Beyne, Erik Jan Marinissen, Dimitrios Velenis, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

Prediction of the Influence of Induced Stresses in Silicon on CMOS Performance in a Cu-Through-Via Interconnect Technology

E. Beyne, G. Eneman, P. Verheyen, 2007, 2007 International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems. EuroSime 2007.

Interconnect technologies for multi-chip modules: high frequency characterization and loss analysis

E. Beyne, J. Peeters, G. Brandli, 1992, ESSDERC '92: 22nd European Solid State Device Research conference.

Thermal stability of copper Through-Silicon Via barriers during IC processing

Eric Beyne, Deniz S. Tezcan, Philippe Soussan, 2011, 2011 IEEE International Interconnect Technology Conference.

Thermal modeling and management in ultrathin chip stack technology

Olivier Vendier, Eric Beyne, S. Pinel, 2002 .

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

E. Beyne, Walter De Raedt, E. Beyne, 2004, IEEE Transactions on Microwave Theory and Techniques.

Multilayer thin-film MCM-D for the integration of high-performance RF and microwave circuits

Steven Brebels, Eric Beyne, Bart Nauwelaers, 2001 .

Full-wave analysis of multiconductor multislot planar guiding structures in layered media

Ezzeldin A. Soliman, Eric Beyne, Guy A. E. Vandenbosch, 2003 .

Numerically efficient spatial-domain moment method for multislot transmission lines in layered media-application to multislot lines in MCM-D technology

Ezzeldin A. Soliman, Eric Beyne, Guy A. E. Vandenbosch, 1999 .

Electrical field induced ageing of polymer light-emitting diodes in an oxygen-rich atmosphere studied by emission microscopy, scanning electron microscopy and secondary ion mass spectroscopy

E. Beyne, J. Gelan, J. D’Haen, 1998 .

Materials and Technology for RF-MEMS

E. Beyne, H. Tilmans, W. D. Raedt, 2004 .

3D Embedding and Interconnection of Ultra Thin (≪ 20 μm) Silicon Dies

E. Beyne, K. Baert, D. Tezcan, 2007, 2007 9th Electronics Packaging Technology Conference.

Ultra thin die embedding technology with 20μm-pitch interconnection

E. Beyne, T. Funaya, T. Buisson, 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

Chip ultra-thinning and embedding technology for autonomous sensors array applications

E. Beyne, Philippe Muller, P. Soussan, 2009, 2009 59th Electronic Components and Technology Conference.

Void-Free Filling of HAR TSVs Using a Wet Alkaline Cu Seed on CVD Co as a Replacement for PVD Cu Seed

Eric Beyne, Kevin Vandersmissen, Yann Civale, 2011 .

Compact transient thermal models for the polymer stud grid array (PSGATM) package

Bart Vandevelde, Eric Beyne, Robert Mertens, 1997 .

Experimental Thermal Characterisation of Electronic Packages in a Fluid Bath Environment

E. Beyne, W. Temmerman, F. Christiaens, 1997 .

Thermal and Thermo-Mechanical Evaluation of a ‘Chip in Moulded Interconnect Device’

Eric Beyne, J. Roggen, Marcel Heerman, 1997 .

Handbook of 3D Integration: Design, Test, and Thermal Management, Volume 4

Liesbet Van der Perre, Eric Beyne, Geert Van der Plas, 2019 .

Numerical comparison of the thermal performance of 3D stacking and Si interposer based packaging concepts

E. Beyne, G. Van der Plas, B. Vandevelde, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

Thermal characterization of the inter-die thermal resistance of hybrid Cu/dielectric wafer-to-wafer bonding

E. Beyne, Soon-Wook Kim, G. Van der Plas, 2016, 2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).

Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and $\mu$ TSVs

E. Beyne, M. Bakir, G. Van der Plas, 2020, IEEE Transactions on Electron Devices.

The Use of BCB and Photo-BCB Dielectric in MCM-D for High Speed Digital and Microwave Applications

E. Beyne, R. V. Hoof, A. Achem, 1995 .

Improved thermal fatigue reliability for flip chip assemblies using redistribution techniques

E. Beyne, B. Vandevelde, 2000, ECTC 2000.

Thermal fatigue reliability analysis of redistributed flip chip assemblies

E. Beyne, B. Vandevelde, B. Vandevelde, 1998, 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).

Unipolar and Bipolar Resonant Tunneling Components

E. Beyne, C. Hoof, G. Borghs, 1997 .

Advances in microwave

E. Beyne, W. Raedt, 2022 .

Heat transfer and pressure drop correlations for direct on-chip microscale jet impingement cooling with alternating feeding and draining jets

E. Beyne, M. Baelmans, V. Cherman, 2022, International Journal of Heat and Mass Transfer.

Recent advances in system integration and MEMS packaging

Eric Beyne, Chris Van Hoof, Koen Snoeckx, 2005 .

Nozzle scaling effects for the thermohydraulic performance of microjet impingement cooling with distributed returns

E. Beyne, M. Baelmans, I. De Wolf, 2020 .

Evaluation of structural degradation in packaged semiconductor components using a transient thermal characterisation technique

E. Beyne, B. Vandevelde, F. Christriaens, 1996 .

Development of underfilling and thermo-compression bonding processes for stacking multi-layer 3D ICs

Eric Beyne, Andy Miller, Gerald Beyer, 2014, Proceedings of the 5th Electronics System-integration Technology Conference (ESTC).

Process development and characterization of 3D multi-die stacking

K. Rebibis, Andy Miller, G. Beyer, 2020, 2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC).

Thermal Management and Processing Optimization for 3D Multi-layer Stacked ICs

E. Beyne, V. Cherman, P. Bex, 2019, 2019 25th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC).

TCB optimization for stacking large thinned dies with 40 and 20 μm pitch microbumps

K. Rebibis, Andy Miller, G. Beyer, 2018, 2018 7th Electronic System-Integration Technology Conference (ESTC).

Impact of the combination of stress buffer layer and wafer level underfill on 3D IC assembly using thermal compression bonding

K. Rebibis, E. Beyne, P. Bex, 2017, 2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition.

Thermal Compression Bonding: Understanding Heat Transfer by in Situ Measurements and Modeling

E. Beyne, E. Sleeckx, V. Cherman, 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

3D IC assembly using thermal compression bonding and wafer-level underfill — Strategies for quality improvement and throughput enhancement

F. Inoue, K. Rebibis, Andy Miller, 2016, 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC).

Comparison of properties of thermo-compression bonded 3D stacks using a liquid and a dry-film wafer level underfills

R. A. Miller, K. Rebibis, E. Beyne, 2015, 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC).

Wafer applied and no flow underfill screening for 3D stacks

K. Rebibis, E. Beyne, B. Swinnen, 2012, 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).

Developing underfill process in screening of no-flow underfill and wafer-applied underfill materials for 3D stacking

R. A. Miller, K. Rebibis, G. Beyer, 2013, 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).

High-Q RF inductors on low resistivity silicon through wafer post-processing

Eric Beyne, W. De Raedt, G. Carchon, 2002 .

3D Wafer-to-Wafer Bonding Thermal Resistance Comparison: Hybrid Cu/dielectric Bonding versus Dielectric via-last Bonding

E. Beyne, J. de Vos, Soon-Wook Kim, 2020, 2020 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).

Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding

E. Beyne, Soon-Wook Kim, V. Cherman, 2017 .

Experimental Characterization of the Vertical and Lateral Heat Transfer in Three-Dimensional Stacked Die Packages

J. D. Vos, E. Beyne, V. Cherman, 2016 .

CIMID, a technology for high density integration of electronic systems

E. Beyne, J. Roggen, R. Van Hoof, 1994, Workshop on MCM and VLSI Packaging Techniques and Manufacturing Technologies.

Statistical Distribution of Through-Silicon via Cu Pumping

E. Beyne, S. Van Huylenbroeck, K. Croes, 2017, IEEE Transactions on Device and Materials Reliability.

Accurate modeling of high-Q spiral inductors in thin-film multilayer technology for wireless telecommunication applications

Steven Brebels, Eric Beyne, Kristof Vaesen, 2001 .

Probabilistic design approach for integrated passive devices in RF applications

E. Beyne, I. De Wolf, S. Donders, 2008, 2008 58th Electronic Components and Technology Conference.

On the Dielectric Material Properties for Thin Film Integrated RF and Microwave Applications

E. Beyne, P. Pieters, S. Brebels, 1999 .

Electrical characterization, modeling and reliability analysis of a via last TSV

E. Beyne, B. Vandevelde, B. Majeed, 2010, 2010 12th Electronics Packaging Technology Conference.

Thermal, Mechanical and Reliability assessment of Hybrid bonded wafers, bonded at 2.5μm pitch

K. Rebibis, G. Beyer, E. Beyne, 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

Thermal Modelling of the Polymer Stud Grid Array (PSGA) Packages

E. Beyne, B. Vandevelde, R. Mertens, 1997 .

Experimental and numerical investigation of direct liquid jet impinging cooling using 3D printed manifolds on lidded and lidless packages for 2.5D integrated systems

E. Beyne, M. Baelmans, V. Cherman, 2020 .

Experimental Characterization of a Chip-Level 3-D Printed Microjet Liquid Impingement Cooler for High-Performance Systems

E. Beyne, M. Baelmans, I. De Wolf, 2019, IEEE Transactions on Components, Packaging and Manufacturing Technology.

High-Efficiency Polymer-Based Direct Multi-Jet Impingement Cooling Solution for High-Power Devices

E. Beyne, M. Baelmans, I. De Wolf, 2019, IEEE Transactions on Power Electronics.

Experimental characterization and model validation of liquid jet impingement cooling using a high spatial resolution and programmable thermal test chip

E. Beyne, M. Baelmans, G. Van der Plas, 2019, Applied Thermal Engineering.

Edge trimming for surface activated dielectric bonded wafers

A. Jourdain, F. Inoue, K. Rebibis, 2017 .

Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects

Eric Beyne, Luka Kljucar, Ingrid De Wolf, 2017, Microelectron. Reliab..

Reliability Study of Polymers Used in Sub-4-μm Pitch RDL Applications

E. Beyne, K. Croes, M. Stucchi, 2021, IEEE Transactions on Components, Packaging and Manufacturing Technology.

First Demonstration of a Low Cost/Customizable Chip Level 3D Printed Microjet Hotspot-Targeted Cooler for High Power Applications

E. Beyne, M. Baelmans, I. De Wolf, 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

Semi-additive Cu-polymer RDL process for interposers applications

E. Beyne, D. Velenis, X. Sun, 2014, Proceedings of the 5th Electronics System-integration Technology Conference (ESTC).

Nanohardness study of CoSn/sub 2/ intermetallic layers formed between CO UBM and Sn flip-chip solder joints

E. Beyne, R. Labie, P. Ratchev, 2004, Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).

Reflow process optimization for micro-bumps applications in 3D technology

Eric Beyne, Erik Jan Marinissen, Andy Miller, 2014, Proceedings of the 5th Electronics System-integration Technology Conference (ESTC).

Thiol‐Based Self‐Assembled Monolayers (SAMs) as an Alternative Surface Finish for 3D Cu Microbumps

F. Inoue, E. Beyne, V. Cherman, 2015 .

Wafer level packaging technology for low-loss on-chip transmission lines and inductors

Eric Beyne, W. De Raedt, G. Carchon, 2003 .

MULTI-LAYER THIN-FILM MCM-D FOR THE INTEGRATION OF HIGH PERFORMANCE WIRELESS FRONT-END SYSTEMS

Eric Beyne, Bart Nauwelaers, Kristof Vaesen, 2001 .

Liquid mediated direct bonding and bond propagation

K. Rebibis, Andy Miller, G. Beyer, 2016, 2016 6th Electronic System-Integration Technology Conference (ESTC).

SAMs (self-assembled monolayers) passivation of cobalt microbumps for 3D stacking of Si chips

K. Rebibis, Andy Miller, E. Beyne, 2016 .

Direct Bonding of low Temperature Heterogeneous Dielectrics

F. Inoue, Andy Miller, G. Beyer, 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

Optical Beam-Based Defect Localization Methodologies for Open and Short Failures in Micrometer-Scale 3-D TSV Interconnects

E. Beyne, J. de Vos, S. Van Huylenbroeck, 2020, IEEE Transactions on Components, Packaging and Manufacturing Technology.

MEMS for wireless communications: ‘from RF-MEMS components to RF-MEMS-SiP’

Eric Beyne, Harrie A.C. Tilmans, Walter De Raedt, 2003 .

Study of wafer warpage for Fan-Out wafer level packaging: finite element modelling and experimental validation

K. Rebibis, E. Beyne, A. Phommahaxay, 2019, 2019 20th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).

Reliability Investigation of W2W Hybrid Bonding Interface: Breakdown Voltage and Leakage Mechanism

E. Beyne, S. Chew, K. Croes, 2022, 2022 IEEE International Reliability Physics Symposium (IRPS).

Physics of self-aligned assembly at room temperature

E. Beyne, V. Dubey, I. Wolf, 2018 .

Investigating moisture diffusion in Mold Compounds (MCs) for Fan-Out-Wafer-Level-Packaging (FOWLP)

E. Beyne, M. Gonzalez, A. Salahouelhadj, 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).

Vapor deposited thin organic–inorganic capping layers preventing copper line oxidation in polymer-based RDL technologies

E. Beyne, E. Walsby, K. Croes, 2022, Microelectronic Engineering.

Development of multi-stack dielectric wafer bonding

A. Jourdain, F. Inoue, Andy Miller, 2016, 2016 17th International Conference on Electronic Packaging Technology (ICEPT).

Process and Material Requirements for Successful Heterogonous Passive Component Integration in RF System

E. Beyne, P. Soussan, G. Carchon, 2006 .

The kinetics of the early stages of electromigration and concurrent temperature induced processes in thin film metallisations studied by means of an in-situ high resolution resistometric technique

E. Beyne, K. Maex, B. Vandevelde, 1999 .

Novel Cu–Cu Bonding Technique: The Insertion Bonding Approach

E. Beyne, B. Vandevelde, C. Okoro, 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Influence of Composition of SiCN as Interfacial Layer on Plasma Activated Direct Bonding

F. Inoue, Andy Miller, G. Beyer, 2019, ECS Journal of Solid State Science and Technology.

Pulsed DC Sputtered Aluminum Nitride: A Novel Approach To Control Stress And C-axis Orientation

E. Beyne, P. Soussan, H. Tilmans, 2004 .

Effects of isothermal storage on grain structure of Cu/Sn/Cu microbump interconnects for 3D stacking

E. Beyne, K. Croes, M. Wolf, 2019, Microelectronics Reliability.

Formation, processing and characterization of Co-Sn intermetallic compounds for potential integration in 3D interconnects

Eric Beyne, Ingrid De Wolf, Bjorn Vandecasteele, 2015 .

Comparison of a Cu UBM versus a Co UBM for Sn Flip-Chip Bumps

E. Beyne, R. Labie, P. Ratchev, 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..

High efficiency direct liquid jet impingement cooling of high power devices using a 3D-shaped polymer cooler

E. Beyne, G. Van der Plas, I. De Wolf, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

CMOS-integrated sige MEMS: Application to micro-mirrors

E. Beyne, A. Witvrouw, I. De Wolf, 2009, TRANSDUCERS 2009 - 2009 International Solid-State Sensors, Actuators and Microsystems Conference.

The Shear Test as Interface Characterization Tool Applied to the Si-BCB Interface

Bart Vandevelde, Eric Beyne, Joris Degrieck, 2009 .

SOP integration and codesign of antennas

E. Beyne, S. Brebels, J. Ryckaert, 2004, IEEE Transactions on Advanced Packaging.

An optimized process for the production of advanced planar wire grid plates as detectors for high energy physics experiments

E. Beyne, F. Iacopi, W. Doninck, 2001 .

Reliability concerns in copper TSV's: Methods and results

E. Beyne, G. Van der Plas, I. De Wolf, 2012, 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

A Novel Intermetallic Compound Insertion Bonding to Improve Throughput for Sequential 3-D Stacking

E. Beyne, I. Wolf, J. Derakhshandeh, 2020, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Investigation of Co UBM for direct bumping on Cu/LowK dies

E. Beyne, R. Labie, P. Ratchev, 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

Electromigration: Investigation of heterogeneous systems

E. Beyne, W. D. Ceuninck, L. Schepper, 1993 .

Solder parameter sensitivity for CSP life-time prediction using simulation-based optimization method

Eric Beyne, J.F.J.M. Caers, B. Vandevelde, 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

Wafer Level Package Integrated Functions

E. Beyne, G. Carchon, 2004 .

Hermal cycling reliability of snagcu and snpb solder joints: a comparison for several ic-packages

Paresh Limaye, Bart Vandevelde, Eric Beyne, 2004, 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, 2004. EuroSimE 2004. Proceedings of the.

Effect of test structure on electromigration characteristics in three-dimensional through silicon via stacked devices

Eric Beyne, Ingrid De Wolf, Joeri De Vos, 2015 .

Residual thermomechanical stresses in thinned-chip assemblies

Olivier Vendier, Eric Beyne, S. Pinel, 2000 .

Impact of the electrodeposition chemistry used for TSV filling on the microstructural and thermo-mechanical response of Cu

Bart Vandevelde, Eric Beyne, Dirk Vandepitte, 2011 .

Analysis of microbump induced stress effects in 3D stacked IC technologies

Diederik Verkest, Bart Vandevelde, Eric Beyne, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

P. Soussan, E. Beyne, A. Mercha, 2010, 2010 International Electron Devices Meeting.

Study of the effect of Sn grain boundaries on IMC morphology in solid state inter-diffusion soldering

E. Beyne, I. De Wolf, N. Moelans, 2019, Scientific Reports.

Study on Process Induced out-of-plane deformation for Fan-Out Wafer Level Packaging

E. Beyne, M. Gonzalez, A. Salahouelhadj, 2020, 2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC).

Outperformance of Cu pillar flip chip bumps in electromigration testing

Bart Vandevelde, Eric Beyne, Riet Labie, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Resistance to electromigration of purely intermetallic micro-bump interconnections for 3D-device stacking

Eric Beyne, Wouter Ruythooren, Riet Labie, 2008, 2008 International Interconnect Technology Conference.

Edge Trimming Induced Defects on Direct Bonded Wafers

A. Jourdain, F. Inoue, K. Rebibis, 2018 .

Analytical Thermo-Mechanical Model for Non-Underfilled Area Array Flip Chip Assemblies

E. Beyne, M. Baelmans, B. Vandevelde, 2004 .

THERMO-MECHANICAL ANALYSIS OF A CHIP SCALE PACKAGE (CSP) USING LEAD FREE AND LEAD CONTAINING SOLDER MATERIALS

E. Beyne, B. Vandevelde, Mario Gonzalez, 2004 .

Influence of printed circuit board properties on solder joint fatigue life of assembled IC packages

Bart Vandevelde, Eric Beyne, Martine Baelmans, 2004 .

Parameterized Modeling of Thermomechanical Reliability for CSP Assemblies

Bart Vandevelde, Martine Baelmans, Dirk Vandepitte, 2003 .

Optimal choice of the FEM damage volumes for estimation of the solder joint reliability for electronic package assemblies

E. Beyne, B. Vandevelde, M. Gonzalez, 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

Thermal fatigue analysis of the flip chip assembly on the polymer stud grid array (PSGA) package

Bart Vandevelde, Eric Beyne, E. Beyne, 1999 .

3D SoC integration, beyond 2.5D chiplets

G. Beyer, E. Beyne, D. Milojevic, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Simulation of Cu bulge-out by cyclic Cu surface diffusion FEM in Cu/SiCN hybrid bonding

E. Beyne, Mario Gonzalez, I. Wolf, 2023, 2023 24th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).

700nm pitch Cu/SiCN wafer-to-wafer hybrid bonding

Andy Miller, G. Beyer, E. Beyne, 2022, 2022 IEEE 24th Electronics Packaging Technology Conference (EPTC).

Integrated high-frequency inductors using amorphous electrodeposited Co-P core

Eric Beyne, Jean-Pierre Celis, Wouter Ruythooren, 2002 .

Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding

Andy Miller, G. Beyer, E. Beyne, 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

Simulation of Cu pad expansion in wafer-to-wafer Cu/SiCN hybrid bonding

E. Beyne, L. Witters, I. De Wolf, 2022, Microelectronics Reliability.

Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects

Eric Beyne, Andy Miller, Joeri De Vos, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

Ultra-Fine Pitch 3D Integration Using Face-to-Face Hybrid Wafer Bonding Combined with a Via-Middle Through-Silicon-Via Process

Eric Beyne, Mikael Detalle, Andy Miller, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics

Eric Beyne, Gerald Beyer, Andy Miller, 2015, 2015 International 3D Systems Integration Conference (3DIC).

W2W permanent stacking for 3D system integration

Eric Beyne, Andy Miller, Herbert Struyf, 2014, 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).

Cu pumping in TSVs: Effect of pre-CMP thermal budget

Bart Vandevelde, Eric Beyne, Ingrid De Wolf, 2011, Microelectron. Reliab..

Characterization of through-silicon vias using laser terahertz emission microscopy

E. Beyne, M. Tonouchi, K. Jacobs, 2021, Nature Electronics.

Modeling Copper Plastic Deformation and Liner Viscoelastic Flow Effects on Performance and Reliability in Through Silicon Via (TSV) Fabrication Processes

E. Beyne, S. Van Huylenbroeck, P. Absil, 2019, IEEE Transactions on Device and Materials Reliability.

Expected Failures in 3-D Technology and Related Failure Analysis Challenges

Eric Beyne, Ingrid De Wolf, Kristof Croes, 2018, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Impact of barrier integrity on liner reliability in 3D through silicon vias

E. Beyne, I. De Wolf, K. Croes, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Demonstration of Package Level 3D-printed Direct Jet Impingement Cooling applied to High power, Large Die Applications

E. Beyne, M. Baelmans, V. Cherman, 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

Integrated magnetic cores in FOWLP and their applications

Andy Miller, E. Beyne, C. Adelmann, 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

Demonstration of a collective hybrid die-to-wafer integration

Andy Miller, G. Beyer, E. Beyne, 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

Photosensitive polymer reliability for fine pitch RDL applications

E. Beyne, K. Croes, M. Stucchi, 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

Highly-conformal plasma-enhanced atomic-layer deposition silicon dioxide liner for high aspect-ratio through-silicon via 3D interconnections

G. Beyer, E. Beyne, A. Redolfi, 2012, 2012 4th Electronic System-Integration Technology Conference.

RF Technologies and Systems

Hendrikus Tilmans, Eric Beyne, G. Carchon, 2009 .

Introducing a silicone under the bump configuration for stress relief in a wafer level package

E. Beyne, B. Vandevelde, H. Meynen, 2003, Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003).

HIGH DENSITY AND HIGH BANDWIDTH CHIP-TO-CHIP CONNECTIONS WITH 20μm PITCH FLIP-CHIP ON FAN-OUT WAFER LEVEL PACKAGE

E. Beyne, A. Phommahaxay, K. Rebibis, 2018, 2018 International Wafer Level Packaging Conference (IWLPC).

A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-µm Pitch

Eric Beyne, Andy Miller, John Slabbekoorn, 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

Optimizing Au and In micro-bumping for 3D chip stacking

E. Beyne, W. Ruythooren, W. Zhang, 2008, 2008 58th Electronic Components and Technology Conference.

Constant impedance scaling paradigm for scaling LC transmission lines

Steven Brebels, Eric Beyne, Bart Nauwelaers, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Constant impedance scaling paradigm for interconnect synthesis

Steven Brebels, Eric Beyne, Bart Nauwelaers, 2006, SLIP '06.

Low-Cost Energy-Efficient On-Chip Hotspot Targeted Microjet Cooling for High- Power Electronics

E. Beyne, M. Baelmans, V. Cherman, 2020, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Modeling the effect of charges in the back side passivation layer on through silicon via (TSV) capacitance after wafer thinning

E. Beyne, J. Raskin, P. Absil, 2015, 2015 IEEE MTT-S International Microwave Symposium.

Carrier Systems for Collective Die-to-Wafer Bonding

G. Beyer, E. Beyne, Alice Guerrero, 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).

Direct Bonding Using Low Temperature SiCN Dielectrics

A. Jourdain, E. Beyne, E. Walsby, 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).

Characterization of bonding activation sequences to enable ultra-low Cu/SiCN wafer level hybrid bonding

F. Inoue, E. Beyne, J. de Vos, 2021, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC).

Acoustic modulation during laser debonding of collective hybrid bonded dies

G. Beyer, E. Beyne, Alice Guerrero, 2021, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC).

Demonstration of a collective hybrid die-to-wafer integration using glass carrier

A. Jourdain, G. Beyer, E. Beyne, 2021, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC).

Introduction of a New Carrier System for Collective Die-to-Wafer Hybrid Bonding and Laser-Assisted Die Transfer

G. Beyer, E. Beyne, Alice Guerrero, 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

A Highly Reliable 1.4μm Pitch Via-Last TSV Module for Wafer-to-Wafer Hybrid Bonded 3D-SOC Systems

Andy Miller, G. Beyer, E. Beyne, 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

A Highly Reliable 1×5μm Via-last TSV Module

Andy Miller, G. Beyer, E. Beyne, 2018, 2018 IEEE International Interconnect Technology Conference (IITC).

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Luca Benini, Federico Angiolini, Paresh Limaye, 2010, IEEE Journal of Solid-State Circuits.

Effect of TSV presence on FEOL yield and reliability

E. Beyne, K. Croes, G. Groeseneken, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Accurate RF electrical characterization of CSPs using MCM-D thin film technology

E. Beyne, W. De Raedt, B. Nauwelaers, 2004, IEEE Transactions on Advanced Packaging.

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias

Eric Beyne, Ingrid De Wolf, Chen Wu, 2014, Microelectron. Reliab..

Microstructure simulation of grain growth in Cu Through Silicon Via using phase-field modeling

Eric Beyne, Christopher J. Wilson, Ingrid De Wolf, 2014, 2014 15th International Conference on Thermal, Mechanical and Mulit-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).

Integrated passives for a DECT VCO

Eric Beyne, Kristof Vaesen, P. Pieters, 2000 .

Analysis and Application of a Surface Admittance Operator for Combined Magnetic and Dielectric Contrast in Emerging Interconnect Topologies

E. Beyne, D. Vande Ginste, N. Pantano, 2023, IEEE Transactions on Microwave Theory and Techniques.

Entire Domain Basis Function Expansion of the Differential Surface Admittance for Efficient Broadband Characterization of Lossy Interconnects

Eric Beyne, Xiao Sun, Dries Vande Ginste, 2020, IEEE Transactions on Microwave Theory and Techniques.

Multimodal characterization of planar microwave structures

E. Beyne, G.A.E. Vandenbosch, E.A. Soliman, 2004, IEEE Transactions on Microwave Theory and Techniques.

Technology Assessment of Through-Silicon Via by Using $C$ – $V$ and $C$ – $t$ Measurements

E. Beyne, W. Dehaene, D. Velenis, 2011 .

Technology Assessment of Through-Silicon Via by Using $C$–$V$ and $C$–

E. Beyne, W. Dehaene, D. Velenis, 2011, IEEE Electron Device Letters.

Bow-tie slot antenna fed by CPW

Ezzeldin A. Soliman, Steven Brebels, Eric Beyne, 1999 .

Compact thermal modeling of hot spots in advanced 3D-stacked ICs

E. Beyne, I. De Wolf, B. Vandevelde, 2009, 2009 11th Electronics Packaging Technology Conference.

Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration

A. Jourdain, Andy Miller, G. Beyer, 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

Novell embedded microbump approach for die-to-die and wafer-to-wafer interconnects with variable microbump diameters and down to 5 um interconnect pitch scaling

F. Inoue, K. Rebibis, G. Beyer, 2019, 2019 22nd European Microelectronics and Packaging Conference & Exhibition (EMPC).

Key elements for sub-50μm pitch micro bump processes

E. Beyne, J. De Vos, C. Gerets, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

3D System Integration Technologies

Eric Beyne, E. Beyne, B. Swinnen, 2006, 2006 International Symposium on VLSI Technology, Systems, and Applications.

Low temperature technology options for integrated high density capacitors

P. Soussan, E. Beyne, L. Goux, 2006, 56th Electronic Components and Technology Conference 2006.

The Growing Application Field of Laser Debonding: From Advanced Packaging to Future Nanoelectronics

Andy Miller, G. Beyer, E. Beyne, 2019, 2019 International Wafer Level Packaging Conference (IWLPC).

MCM-D technology for integrated passives components

E. Beyne, W. De Raedt, P. Pieters, 2000, ICM'99. Proceedings. Eleventh International Conference on Microelectronics (IEEE Cat. No.99EX388).

Comparison of x-ray diffraction, wafer curvature and Raman spectroscopy to evaluate the stress evolution in Copper TSV's

E. Beyne, A. Redolfi, V. Simons, 2012, 2012 IEEE International Interconnect Technology Conference.

Micro-Scale Jet Cooling: A Numerical Study on Improvement Options

E. Beyne, I. De Wolf, V. Cherman, 2023, 2023 22nd IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).

Dielectric liner reliability in via-middle through silicon vias with 3 Micron diameter

G. Beyer, E. Beyne, K. Croes, 2016 .

Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration

E. Beyne, E. Sleeckx, W. Dehaene, 2011 .

Design of an optimal heat-sink geometry for forced convection air cooling of Multi-Chip Modules

Eric Beyne, Jan Berghmans, B Boesmans, 1994 .

The rise of the 3rd dimension for system intergration

E. Beyne, E. Beyne, 2006, 2006 International Interconnect Technology Conference.

Electro-migration behavior of Pb-free Flip Chip Bumps

E. Beyne, B. Swinnen, R. Labie, 2006 .

Growth rate of IMC in the binary sytems of Co/Sn and Cu/Sn

S. H. Sharifi, K. Rebibis, Andy Miller, 2017, 2017 IEEE International Interconnect Technology Conference (IITC).

Recent Advances in 3D Integration at IMEC

Eric Beyne, Chris Van Hoof, Philippe Soussan, 2006 .

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

A. Jourdain, G. Beyer, E. Beyne, 2020, ECS Journal of Solid State Science and Technology.

NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips

E. Beyne, J. Abella, D. Ielmini, 2023, 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Non-destructive In-line IMC Thickness Measurement Using Acoustic Metrology for 3D Stacking

Andy Miller, E. Beyne, M. Kotelyanskii, 2019, International Symposium on Microelectronics.

Performance and Reliability Impact of Copper Plasticity in Backside TSV-Last Fabrication Process

E. Beyne, S. Van Huylenbroeck, Xiaopeng Xu, 2016, IEEE Transactions on Device and Materials Reliability.

Analysis of copper plasticity impact in TSV-middle and backside TSV-last fabrication processes

E. Beyne, S. Van Huylenbroeck, Xiaopeng Xu, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Thermo-mechanics of 3D-wafer level and 3D stacked IC packaging technologies

E. Beyne, B. Vandevelde, B. Swinnen, 2008, EuroSimE 2008 - International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems.

3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)

Eric Beyne, Wim Dehaene, Anne Jourdain, 2009, 2009 IEEE International Conference on 3D System Integration.

Impact of 3D design choices on manufacturing cost

Eric Beyne, Erik Jan Marinissen, Dimitrios Velenis, 2009, 2009 IEEE International Conference on 3D System Integration.

Thermo-mechanical design of a generic 0-level MEMS package using chip capping and Through Silicon Via's

E. Beyne, R. Jansen, B. Vandevelde, 2010, 2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE).

THE RISE OF THE 3 RD DIMENSION FOR SYSTEM INTEGRATION

Eric Beyne, E. Beyne, 2006 .

Design and Technology Solutions for 3D Integrated High Performance Systems

Eric Beyne, Geert Van der Plas, E. Beyne, 2021, 2021 Symposium on VLSI Circuits.

Cost components for 3D system integration

Eric Beyne, Erik Jan Marinissen, Anne Jourdain, 2014, Proceedings of the 5th Electronics System-integration Technology Conference (ESTC).

Impact of Via Density on the Mechanical Integrity of Advanced Back-End-of-Line During Packaging

Eric Beyne, Ingrid De Wolf, Mario Gonzalez, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Convolution based compact thermal model application to the evaluation of the thermal impact of die to die interface including interconnections

E. Beyne, M. Baelmans, I. De Wolf, 2014, Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).

A MCM-D-type module for the ATLAS pixel detector

E. Beyne, K. Becks, P. Gerlach, 1998, 1998 IEEE Nuclear Science Symposium Conference Record. 1998 IEEE Nuclear Science Symposium and Medical Imaging Conference (Cat. No.98CH36255).

Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

E. Beyne, N. Horiguchi, I. Radu, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via

G. Beyer, E. Beyne, K. Croes, 2017 .

Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route

Peter Debacker, Dragomir Milojevic, Eric Beyne, 2019, 2019 International 3D Systems Integration Conference (3DIC).

Thermal Modeling and Model Validation for 3D Stacked ICs

E. Beyne, V. Cherman, H. Oprins, 2019, Handbook of 3D Integration.

Extending the roadmap beyond 3nm through system scaling boosters: A case study on Buried Power Rail and Backside Power Delivery

J. Ryckaert, A. Gupta, A. Jourdain, 2019, 2019 Electron Devices Technology and Manufacturing Conference (EDTM).

"Hole-in-One TSV", a New Via Last Concept for High Density 3D-SOC Interconnects

Eric Beyne, Anne Jourdain, Andy Miller, 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

Convolution-Based Fast Thermal Model for 3-D-ICs: Transient Experimental Validation

Eric Beyne, Martine Baelmans, Vladimir Cherman, 2017, IEEE Transactions on Components, Packaging and Manufacturing Technology.

3D-convolution based fast transient thermal model for 3D integrated circuits: methodology and applications

Eric Beyne, Martine Baelmans, Ingrid De Wolf, 2015, 2015 31st Thermal Measurement, Modeling & Management Symposium (SEMI-THERM).

Reliability Challenges Related to TSV Integration and 3-D Stacking

Eric Beyne, Wei Guo, Ingrid De Wolf, 2016, IEEE Design & Test.

Process technology for the fabrication of a Chip-in-Wire style packaging

C. Van Hoof, F. Iker, P. Soussan, 2008, 2008 58th Electronic Components and Technology Conference.

Active Electrode Arrays by Chip Embedding in a Flexible Silicone Carrier

Eric Beyne, Mario Gonzalez, Kris Baert, 2006, 2006 International Conference of the IEEE Engineering in Medicine and Biology Society.

Thermal analysis of 3D functional partitioning for high-performance systems

E. Beyne, H. Oprins, D. Milojevic, 2021, 2021 20th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm).

Fast Transient Convolution-Based Thermal Modeling Methodology for Including the Package Thermal Impact in 3D ICs

Eric Beyne, Martine Baelmans, Ingrid De Wolf, 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Fast convolution based thermal model for 3D-ICs: Methodology, accuracy analysis and package impact

Eric Beyne, Martine Baelmans, Ingrid De Wolf, 2014, Microelectron. J..

Impact of gate-level clustering on automated system partitioning of 3D-ICs

E. Beyne, G. V. D. Plas, D. Milojevic, 2023, Microelectron. J..

Advances in Temporary Carrier Technology for High-Density Fan-Out Device Build-up

Andy Miller, G. Beyer, E. Beyne, 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

Advances in Temporary Bonding and Release Technology for Ultrathin Substrate Processing and High-Density Fan-Out Device Build-up

G. Beyer, E. Beyne, E. Sleeckx, 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

Buried Power Rails and Nano-Scale TSV: Technology Boosters for Backside Power Delivery Network and 3D Heterogeneous Integration

A. Jourdain, G. Beyer, E. Beyne, 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).

Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)

Eric Beyne, Dragomir Milojevic, Geert Van der Plas, 2021, 2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

Advances in Thin Wafer Debonding and Ultrathin 28-nm FinFET Substrate Transfer

A. Jourdain, G. Beyer, E. Beyne, 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

Extremely Low-Force Debonding of Thinned CMOS Substrate by Laser Release of a Temporary Bonding Material

G. Beyer, E. Beyne, E. Sleeckx, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Single-release-layer process for temporary bonding applications in the 3D integration area

A. Jourdain, K. Rebibis, Andy Miller, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Process characterization of thin wafer debonding with thermoplastic materials

A. Jourdain, Andy Miller, G. Beyer, 2012, 2012 4th Electronic System-Integration Technology Conference.

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Eric Beyne, Rama Puligadda, Anne Jourdain, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Temporary wafer bonding defect impact assessment on substrate thinning: Process enhancement through systematic defect track down

E. Beyne, A. Jourdain, S. Suhard, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, IEEE Transactions on Electron Devices.

Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster

A. Jourdain, G. Beyer, E. Beyne, 2021, 2021 Symposium on VLSI Technology.

Technology optimization for high bandwidth density applications on 3D interposer

Marian Verhelst, Eric Beyne, Mikael Detalle, 2016, 2016 6th Electronic System-Integration Technology Conference (ESTC).

IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and μ- & n- TSVs

E. Beyne, J. Ryckaert, P. Weckx, 2021, 2021 IEEE International Interconnect Technology Conference (IITC).

Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

A. Jourdain, E. Beyne, A. Veloso, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Package level thermal analysis of backside power delivery network (BS-PDN) configurations

E. Beyne, H. Oprins, B. Vermeersch, 2022, 2022 21st IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm).

Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper

E. Beyne, P. Weckx, O. Zografos, 2022, Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding.

Backside power delivery as a scaling knob for future systems

Eric Beyne, Julien Ryckaert, Pieter Weckx, 2019, Advanced Lithography.

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node

A. Jourdain, E. Beyne, A. Veloso, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Power from Below: Buried Interconnects Will Help Save Moore's Law

E. Beyne, B. Cline, O. Zografos, 2021, IEEE Spectrum.

Thermal Performance Comparison of Advanced 3D Packaging Concepts for Logic and Memory Integration in Mobile Cooling Conditions

E. Beyne, V. Cherman, H. Oprins, 2018, 2018 17th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).

Characterization of the thermal impact of Cu-Cu bonds achieved using TSVs on hot spot dissipation in 3D stacked ICs

E. Beyne, G. Van der Plas, V. Cherman, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Thermal test vehicle for the validation of thermal modelling of hot spot dissipation in 3D stacked ICs

E. Beyne, V. Cherman, M. Stucchi, 2010, 3rd Electronics System Integration Technology Conference ESTC.

Thermal analysis of hot spots in advanced 3D-stacked structures

E. Beyne, I. De Wolf, B. Vandevelde, 2009, 2009 15th International Workshop on Thermal Investigations of ICs and Systems.

3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes

E. Beyne, J. Ryckaert, M. Stucchi, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Inorganic capping layers in advanced photosensitive polymer based RDL processes: processing and reliability

Andy Miller, E. Beyne, J. Slabbekoorn, 2023, 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC).

Cobalt-Tin Intermetallic Compounds as Alternative Surface Finish for Low Temperature Die-to-Wafer Solder Stacking

F. Inoue, E. Beyne, J. Derakhshandeh, 2021, International Conference on Electronics Packaging.

Novel Temporary Bonding and Debonding Solutions Enabling an Ultrahigh Interonnect Density Fo-Wlp Structure Assembly with Quasi-Zero Die Shift

K. Rebibis, Andy Miller, G. Beyer, 2019, 2019 International Wafer Level Packaging Conference (IWLPC).

Material technology for 2.5D/3D package

K. Rebibis, Andy Miller, E. Beyne, 2015, 2015 IEEE CPMT Symposium Japan (ICSJ).

Insights into Scaled Logic Devices Connected from Both Wafer Sides

A. Jourdain, E. Beyne, A. De Keersgieter, 2022, International Electron Devices Meeting.

Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network

A. Jourdain, E. Beyne, A. Veloso, 2022, International Electron Devices Meeting.

Cost-effective RF interposer platform on low-resistivity Si enabling heterogeneous integration opportunities for beyond 5G

E. Beyne, N. Collaert, D. Velenis, 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).

Advances in Photosensitive Polymer Based Damascene RDL Processes: Toward Submicrometer Pitches With More Metal Layers

Andy Miller, E. Beyne, J. Slabbekoorn, 2021, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC).

Enabling Ultra-Thin Die to Wafer Hybrid Bonding for Future Heterogeneous Integrated Systems

F. Inoue, G. Beyer, E. Beyne, 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

Reliability Investigations of Polymer Based Redistribution Layers (RDL) Protected by a Mold Layer

E. Beyne, J. De Messemaeker, J. Slabbekoorn, 2023, 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC).

Broadband Characterization of Polymers under Reliability Stresses and Impact of Capping Layer

E. Beyne, N. Pantano, M. O. de Beeck, 2022, Electronic Components and Technology Conference.

Application of the surface planer process to Cu pillars and wafer support tape for high-coplanarity wafer-level packaging

F. Inoue, E. Beyne, A. Phommahaxay, 2022, The International Journal of Advanced Manufacturing Technology.

84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor

E. Beyne, F. Catthoor, R. Lauwereins, 2022, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Ultra-Fine Pitch RDL (UFPRDL) using Polymer Dual Damascene processing

Andy Miller, E. Beyne, J. Slabbekoorn, 2023, Electronic Components and Technology Conference.

Tbps/mm bandwidth for chip-to-chip communication using fine pitch damascene RDL

E. Beyne, J. Slabbekoorn, N. Pantano, 2020, 2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC).

What’s in Space – Exploration and Improvement of Line/Space Defect Inspection of Fine-Pitch Redistribution Layer for Fan-Out Wafer Level Packaging

E. Beyne, M. Liebens, A. Miller, 2019, 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

Liquid jet impingement cooling of high-performance interposer packages: a hybrid CFD – FEM modeling study

E. Beyne, V. Cherman, H. Oprins, 2023, Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.

Film Characterization of Low-Temperature Silicon Carbon Nitride for Direct Bonding Applications

E. Beyne, E. Sleeckx, A. Phommahaxay, 2020, ECS Journal of Solid State Science and Technology.

10 and 7 μm Pitch Thermo-compression Solder Joint, Using A Novel Solder Pillar And Metal Spacer Process

F. Inoue, Andy Miller, G. Beyer, 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

Inorganic Capping Layers in RDL Technologies: Process Advantages and Reliability

E. Beyne, J. Slabbekoorn, S. Armini, 2023, JOM.

Experimental thermal characterization and thermal model validation of 3D packages using a programmable thermal test chip

E. Beyne, J. de Vos, V. Cherman, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Thermal Analysis of Polymer 3D Printed Jet Impingement Coolers for High Performance 2.5D Si Interposer Packages

E. Beyne, M. Baelmans, I. De Wolf, 2019, 2019 18th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).

Convolution based compact thermal model for 3D-ICs: Methodology and accuracy analysis

Eric Beyne, Ingrid De Wolf, Herman Oprins, 2013, 19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC).

Impact of 1μ m TSV via-last integration on electrical performance of advanced FinFET devices

Eric Beyne, Jerome Mitard, Ben Kaczer, 2018, 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM).

Evolution of temporary wafer (de)bonding technology towards low temperature processes for enhanced 3D integration

A. Jourdain, G. Beyer, E. Beyne, 2012, 2012 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration.

Low Warpage Wafer Level Transfer Molding Post 3D Die to Wafer Assembly

K. Rebibis, G. Beyer, E. Beyne, 2016, Electronic Components and Technology Conference.

Fine-pitch bonding technology with surface-planarized solder micro-bump/polymer hybrid for 3D integration

F. Inoue, E. Beyne, M. Lofrano, 2021 .

Morphological characterization and mechanical behavior by dicing and thinning on direct bonded Si wafer

F. Inoue, K. Rebibis, E. Beyne, 2020 .

Influence of Si wafer thinning processes on (sub)surface defects

A. Jourdain, J. D. Vos, F. Inoue, 2017 .

Wafer reconstruction: An alternative 3D integration process flow

Eric Beyne, Jose Luis Silva, Mario Gonzalez, 2013, 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).

System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs

E. Beyne, G. Kar, J. Ryckaert, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Characterization of inorganic dielectric layers for low thermal budget wafer-to-wafer bonding

F. Inoue, G. Beyer, E. Beyne, 2017, 2017 5th International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D).

Measurements and Analysis of Substrate Noise Coupling in TSV-Based 3-D Integrated Circuits

Eric Beyne, Paul Marchal, Makoto Nagata, 2014, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Evaluation of Mechanical Stress Induced During IC Packaging

K. Rebibis, E. Beyne, V. Cherman, 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

Bart Vandevelde, Eric Beyne, Geert Van der Plas, 2012, 2012 IEEE International Conference on IC Design & Technology.

The unique properties of SiCN as bonding material for hybrid bonding

F. Inoue, E. Beyne, Soon-Wook Kim, 2021, 2021 7th International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D).

Advances in SiCN-SiCN Bonding with High Accuracy Wafer-to-Wafer (W2W) Stacking Technology

F. Inoue, G. Beyer, E. Beyne, 2018, 2018 IEEE International Interconnect Technology Conference (IITC).

Area-Selective Electroless Deposition of Cu for Hybrid Bonding

F. Inoue, E. Beyne, Soon-Wook Kim, 2021, IEEE Electron Device Letters.

Demonstration of a novel low cost single material temporary bond solution for high topography substrates based on a mechanical wafer debonding and innovative adhesive removal

A. Jourdain, G. Beyer, E. Beyne, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Origin of Voids at the SiO2/SiO2 and SiCN/SiCN Bonding Interface Using Positron Annihilation Spectroscopy and Electron Spin Resonance

F. Inoue, G. Beyer, E. Beyne, 2023, ECS Journal of Solid State Science and Technology.

Protective Layer for Collective Die to Wafer Hybrid Bonding

Eric Beyne, Alain Phommahaxay, Samuel Suhard, 2019, 2019 International 3D Systems Integration Conference (3DIC).

Advanced Dicing Technologies for Combination of Wafer to Wafer and Collective Die to Wafer Direct Bonding

F. Inoue, Andy Miller, E. Beyne, 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

Efficient Backside Power Delivery for High-Performance Computing Systems

E. Beyne, F. Catthoor, R. Lauwereins, 2022, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Minimizing interposer warpage by process control and design optimization

M. Gonzalez, E. Beyne, Mikael Detalle, 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

Experimental and Numerical Study of 3-D Printed Direct Jet Impingement Cooling for High-Power, Large Die Size Applications

E. Beyne, M. Baelmans, V. Cherman, 2021, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Experimental Characterization of the Vertical and Lateral Heat Transfer in 3D-SIC Packages

Eric Beyne, Geert Van der Plas, Joeri De Vos, 2015 .

Low temperature SiCN as dielectric for hybrid bonding

A. Jourdain, E. Beyne, E. Walsby, 2023, 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM).

TSV process-induced MOS reliability degradation

Eric Beyne, Yunlong Li, Geert Van der Plas, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

Modified micro-macro thermo-mechanical modelling of ceramic ball grid array packages

Alcatel Bell, Geert Willems, Bart Vandevelde, 2003, Microelectron. Reliab..

Broadband modeling and transient analysis of MCM interconnections

E. Beyne, J. Peeters, E. Beyne, 1994 .

Transmission line analysis of MCM interconnects

Eric Beyne, J. Peeters, E. Beyne, 1993, Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93).

A broad band loss model for MCM interconnections

E. Beyne, G. Brandli, J. Peeters, 1993, Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93.

In-line metrology and inspection for process control during 3D stacking of IC's

Eric Beyne, Sandip Halder, Mireille Maenhoudt, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Technologies for highly miniaturized autonomous sensor networks

Refet Firat Yazicioglu, Chris Van Hoof, Vladimir Leonov, 2006, Microelectron. J..

Fabrication and Electrical Evaluation of Via Last Polymer Liner TSVs

E. Beyne, Y. Civale, B. Majeed, 2010 .

Spin-on dielectric liner TSV for 3D wafer level packaging applications

E. Beyne, Y. Civale, B. Majeed, 2010, 2010 IEEE International Interconnect Technology Conference.

Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping

Eric Beyne, Rahul Agarwal, Philippe Soussan, 2009, 2009 IEEE International Conference on 3D System Integration.

Use of Wafer Applied Underfill for 3D Stacking

Eric Beyne, Antonio La Manna, C. Gerets, 2011 .

Electrically yielding Collective Hybrid Bonding for 3D stacking of ICs

Eric Beyne, Anne Jourdain, Philippe Soussan, 2009, 2009 59th Electronic Components and Technology Conference.

Investigation of Co Thin Film as Buffer Layer Applied to Cu/Sn Eutectic Bonding and UBM With Sn, SnCu, and SAC Solders Joints

K. Rebibis, E. Beyne, Kuan-Neng Chen, 2017, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Die to wafer 3D stacking for below 10um pitch microbumps

Teng Wang, Eric Beyne, Anne Jourdain, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

Impact of ELD layers in mechanical properties of microbumps for 3D stacking

K. Rebibis, Andy Miller, E. Beyne, 2016, 2016 6th Electronic System-Integration Technology Conference (ESTC).

Wafer-level package interconnect options

Steven Brebels, Eric Beyne, Bart Nauwelaers, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On the thermal stability of physically-vapor-deposited diffusion barriers in 3D Through-Silicon Vias during IC processing

E. Beyne, A. Redolfi, K. Croes, 2013 .

Fine Pitch Rapid Heat Self-Aligned Assembly and Liquid-Mediated Direct Bonding of Si Chips

Eric Beyne, Jean-Pierre Celis, Ingrid De Wolf, 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices

Eric Beyne, Ingrid De Wolf, Mario Gonzalez, 2017, Microelectron. Reliab..

Design issues and considerations for low-cost 3D TSV IC technology

Paresh Limaye, Bart Vandevelde, Eric Beyne, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices — Technology directions

Eric Beyne, E. Beyne, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Elimination Of The Axial Deformation Problem Of Cu-TSV In 3D Integration

Bart Vandevelde, Eric Beyne, Cedric Huyghebaert, 2010 .

Thermal compression bonding of 20 μm pitch micro bumps with pre-applied underfill - Process and reliability

K. Rebibis, E. Beyne, V. Simons, 2015, 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC).

Methodologies to mitigate package induced stresses in the BEOL

Eric Beyne, Mario Gonzalez, Luka Kljucar, 2016, 2016 6th Electronic System-Integration Technology Conference (ESTC).

Impact of backside process on high aspect ratio via-middle Cu through silicon via reliability

G. Beyer, E. Beyne, J. de Vos, 2017, 2017 International Conference on Electronics Packaging (ICEP).

Hydrogen outgassing induced liner/barrier reliability degradation in through silicon via's

Eric Beyne, Ingrid De Wolf, Stefaan Van Huylenbroeck, 2014 .

Bonding on Cu: a new stress evaluation approach by Raman spectroscopy

C. J. Vath, E. Beyne, I. De Wolf, 2002, 4th Electronics Packaging Technology Conference, 2002..

Simulation of Cu pumping during TSV fabrication

E. Beyne, I. De Wolf, K. Croes, 2013, 2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).