S. Wilton

发表

Tradeoffs in two-level on-chip caching

N. Jouppi, S. Wilton, 1994, Proceedings of 21 International Symposium on Computer Architecture.

Reconfigurable Computing : Architectures , Design Methods , and Applications

S. Wilton, W. Luk, G. Constantinides, 2005 .

On evaluating signal selection algorithms for post-silicon debug

Steven J. E. Wilton, Eddie Hung, S. Wilton, 2011, 2011 12th International Symposium on Quality Electronic Design.

Floating Point FPGAs

Wayne Luk, Philip H. W. Leong, Chi Wai Yu, 2008 .

T-RECX: Tiny-Resource Efficient Convolutional Neural Networks with Early-Exit

N. Ghanathe, S. Wilton, 2022, 2207.06613.

Using data-mining techniques to improve combinatorial optimization algorithms

S. Wilton, P. Jamieson, Farnaz Gharibian, 2022, Journal of Algorithms & Computational Technology.

Algorithms for Embedding Quantum-Dot Cellular Automata Networks onto a Quantum Annealing Processor

S. Wilton, Aidan Roy, M. Babcock, 2017, 1709.04972.

Concentrator access networks for programmable logic cores on SoCs

Steven J. E. Wilton, Bradley R. Quinton, S. Wilton, 2005, 2005 IEEE International Symposium on Circuits and Systems.

WRL Research Report 93/5: An Enhanced Access and Cycle Time Model for On-chip Caches

Norman P. Jouppi, Steven J. E. Wilton, N. Jouppi, 1994 .

Dynamic voltage scaling for commercial FPGAs

Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton, 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

Reconfigurable computing: architectures and design methods

Wayne Luk, Steven J. E. Wilton, Peter Y. K. Cheung, 2005 .

Architectures and algorithms for field-programmable gate arrays with embedded memory

Steven J. E. Wilton, Jonathan Rose, Zvenko Vranesic, 1997 .

Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs

Steven J. E. Wilton, Daniel Holanda Noronha, Kahlan Gibson, 2020, 2020 30th International Conference on Field-Programmable Logic and Applications (FPL).

FPGA Architecture Exploration for DNN Acceleration

Philip H. W. Leong, S. Wilton, Seyedramin Rasoulinezhad, 2022, ACM Trans. Reconfigurable Technol. Syst..

Rethinking Embedded Blocks for Machine Learning Applications

Philip H. W. Leong, S. Wilton, Seyedramin Rasoulinezhad, 2022, ACM Trans. Reconfigurable Technol. Syst..

System-on-Chip: Reuse and Integration

Shahriar Mirabbasi, Guy Lemieux, Alan J. Hu, 2006, Proceedings of the IEEE.

Limitations of incremental signal-tracing for FPGA debug

Steven J. E. Wilton, Eddie Hung, S. Wilton, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

Post-Silicon Debug of Complex Multi Clock and Power Domain ICs

Bradley R. Quinton, Steven J.E. Wilton, S. Wilton, 2010 .

Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays

Steven J. E. Wilton, Jeffrey B. Goeders, Al-Shahna Jamal, 2020, ACM Trans. Reconfigurable Technol. Syst..

In-circuit tuning of deep learning designs

Wayne Luk, Zhiqiang Que, Xinyu Niu, 2021, J. Syst. Archit..

Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs

S. Wilton, W. Luk, Zhiqiang Que, 2020, 2020 International Conference on Field-Programmable Technology (ICFPT).

An Overlay for Rapid FPGA Debug of Machine Learning Applications

Zhiqiang Que, Wayne Luk, Steven J. E. Wilton, 2019, 2019 International Conference on Field-Programmable Technology (ICFPT).

Towards In-Circuit Tuning of Deep Learning Designs

Zhiqiang Que, Wayne Luk, Daniel Holanda Noronha, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

On-chip FPGA Debug Instrumentation for Machine Learning Applications

Wayne Luk, Steven J. E. Wilton, Jeffrey B. Goeders, 2019, FPGA.

An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug

Steven J. E. Wilton, Jeffrey B. Goeders, Al-Shahna Jamal, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

Rapid circuit-specific inlining tuning for FPGA high-level synthesis

Steven J. E. Wilton, Jose P. Pinilla, Daniel H. Noronha, 2017, 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits

Steven J. E. Wilton, Jeffrey B. Goeders, S. Wilton, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An analytical model describing the relationships between logic architecture and FPGA density

Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton, 2008, 2008 International Conference on Field Programmable Logic and Applications.

Runtime-Controlled Energy Reduction Techniques for FPGAs

Steven J. E. Wilton, Assem A. M. Bsoul, Stuart Dueck, 2016 .

Effective FPGA debug for high-level synthesis generated circuits

Steven J. E. Wilton, Jeffrey B. Goeders, S. Wilton, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

An FPGA with power-gated switch blocks

Steven J. E. Wilton, Assem A. M. Bsoul, S. Wilton, 2012, 2012 International Conference on Field-Programmable Technology.

A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs

Steven J. E. Wilton, Assem A. M. Bsoul, S. Wilton, 2012, FPGA '12.

An FPGA architecture supporting dynamically controlled power gating

Steven J. E. Wilton, Assem A. M. Bsoul, S. Wilton, 2010, 2010 International Conference on Field-Programmable Technology.

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

Wayne Luk, Steven J. E. Wilton, Kuen Hung Tsoi, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Flexible Power Model for FPGAs

Steven J. E. Wilton, Andy Yan, K. K. Poon, 2002, FPL.

CACTI: an enhanced cache access and cycle time model

Norman P. Jouppi, Steven J. E. Wilton, N. Jouppi, 1996, IEEE J. Solid State Circuits.

Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm

Rabab Kreidieh Ward, Resve A. Saleh, Steven J. E. Wilton, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks pdf

Steven J. E. Wilton, Daniel H. Noronha, Bahar Salehpour, 2018, ArXiv.

MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications

Vivek Seshadri, Steve Wilton, Aayan Kumar, 2021, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL).

Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs

Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton, 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

FPGA clock network architecture: flexibility vs. area and power

Steven J. E. Wilton, Julien Lamoureux, S. Wilton, 2006, FPGA '06.

Design considerations for soft embedded programmable logic cores

R. Saleh, S.J.E. Wilton, J.C.H. Wu, 2005, IEEE Journal of Solid-State Circuits.

Implementing logic in FPGA memory arrays: heterogeneous memory architectures

Steven J. E. Wilton, S. Wilton, 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques

Steven J. E. Wilton, Rebecca Cheng, Andy Yan, 2002, FPGA '02.

A New Switch Block for Segmented FPGAs

Steven J. E. Wilton, M. Imran Masud, S. Wilton, 1999, FPL.

Implementing logic in FPGA embedded memory arrays: architectural implications

Steven J. E. Wilton, S. Wilton, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays

Steven J. E. Wilton, S. Wilton, 1998, FPGA '98.

An SRAM-programmable field-configurable memory

Steven J. E. Wilton, Jonathan Rose, T. Ngai, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

Architecture of Centralized Field-Configurable Memory

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic, 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays

Steven J. E. Wilton, S. Wilton, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

T-RecX: Tiny-Resource Efficient Convolutional neural networks with early-eXit

N. Ghanathe, S. Wilton, 2022, CF.

Product-term-based synthesizable embedded programmable logic cores

Steven J. E. Wilton, Andy Yan, S. Wilton, 2003, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Boosting Domain-Specific Debug Through Inter-frame Compression

S. Wilton, D. H. Noronha, Zakary Nafziger, 2022, 2022 International Conference on Field-Programmable Technology (ICFPT).

Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs

Wayne Luk, Zhiqiang Que, Steven J. E. Wilton, 2021, 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Architecture Exploration for HLS-Oriented FPGA Debug Overlays

Steven J. E. Wilton, Jeffrey B. Goeders, Al-Shahna Jamal, 2018, FPGA.

Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques

Steven J. E. Wilton, Jeffrey B. Goeders, Pavan Kumar Bussa, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges pdf

Steven J. E. Wilton, Fatemeh Eslami, Eddie Hung, 2016, ArXiv.

An adaptive virtual overlay for fast trigger insertion for FPGA debug

Steven J. E. Wilton, Fatemeh Eslami, S. Wilton, 2015, 2015 International Conference on Field Programmable Technology (FPT).

Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry

Steven J. E. Wilton, Jeffrey B. Goeders, Eddie Hung, 2014, ARC.

Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs)

S. Wilton, Usman Ahmed, Guy Lemieux, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Area, delay, power, and cost trends for metal-programmable structured ASICs (MPSAs)

Steven J.E. Wilton, Guy G.F. Lemieux, Usman Ahmed, 2009, 2009 International Conference on Field-Programmable Technology.

Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices

Steven J. E. Wilton, Fatemeh Eslami, Eddie Hung, 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

BackSpace: Formal Analysis for Post-Silicon Debug

Alan J. Hu, Flavio M. de Paula, Marcel Gort, 2008, 2008 Formal Methods in Computer-Aided Design.

Structural analysis and generation of synthetic digital circuits with memory

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Selected Citation in IEEE Transactions on VLSI Systems

R. F. DeMara, Z. Vranesic, S. Wilton, 2001 .

Layout-Aware Embedding for Quantum Annealing Processors

Steven J. E. Wilton, Jose P. Pinilla, S. Wilton, 2019, ISC.

Steven J. E. Wilton, Zion S. Kwok, Zion Kwok, 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

Practical Asynchronous Interconnect Network Design

Mark R. Greenstreet, Steven J. E. Wilton, Bradley R. Quinton, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A novel FPGA architecture supporting wide, shallow memories

Steven J. E. Wilton, Steven W. Oldridge, S. Wilton, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A detailed power model for field-programmable gate arrays

Steven J. E. Wilton, Andy Yan, K. K. Poon, 2005, TODE.

A novel FPGA architecture supporting wide shallow memories

Steven J. E. Wilton, S. W. Oldridge, S. Wilton, 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays

Steven J. E. Wilton, Julien Lamoureux, S. Wilton, 2005, J. Low Power Electron..

On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays

Steven J. E. Wilton, Scott Y. L. Chin, Clarence S. P. Lee, 2008, Int. J. Reconfigurable Comput..

VersaPower: Power estimation for diverse FPGA architectures

Steven J. E. Wilton, Jeffrey B. Goeders, S. Wilton, 2012, 2012 International Conference on Field-Programmable Technology.

Activity Estimation for Field-Programmable Gate Arrays

Steven J. E. Wilton, Julien Lamoureux, S. Wilton, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug

Steven J. E. Wilton, Fatemeh Eslami, S. Wilton, 2018, ACM Trans. Design Autom. Electr. Syst..

An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug

Steven J. E. Wilton, Fatemeh Eslami, S. Wilton, 2017, CARN.

Incremental distributed trigger insertion for efficient FPGA debug

Steven J. E. Wilton, Fatemeh Eslami, S. Wilton, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs

Steven J. E. Wilton, Rehan Ahmed, Peter Hallschmid, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Maximum flow algorithms for maximum observability during FPGA debug

Steven J. E. Wilton, Eddie Hung, Al-Shahna Jamal, 2013, 2013 International Conference on Field-Programmable Technology (FPT).

Towards development of an analytical model relating FPGA architecture parameters to routability

S. Wilton, Joydip Das, 2013, TRETS.

Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation

Steven J. E. Wilton, Lesley Shannon, Scott Y. L. Chin, 2012, TECS.

Optimizing Floating Point Units in Hybrid FPGAs

Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Accelerated FPGA architecture design: Capabilities and limitations of analytical models

Steven J. E. Wilton, Joydip Das, S. Wilton, 2011, 2011 International Conference on Field-Programmable Technology.

An Analytical Model Relating FPGA Architecture to Logic Density and Depth

S. Wilton, W. Luk, P. Leong, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition

Guy Lemieux, Steven J. E. Wilton, Jeffrey B. Goeders, 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

Towards scalable FPGA CAD through architecture

Steven J. E. Wilton, Scott Y. L. Chin, S. Wilton, 2011, FPGA '11.

An analytical model relating FPGA architecture parameters to routability

Steven J. E. Wilton, Joydip Das, S. Wilton, 2011, FPGA '11.

The impact of interconnect architecture on via-programmed structured ASICs (VPSAs)

Guy Lemieux, Steven J. E. Wilton, Usman Ahmed, 2010, FPGA '10.

Floating-Point FPGA: Architecture and Modeling

Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A detailed delay path model for FPGAs

Philip Heng Wai Leong, Haile Yu, Steven J. E. Wilton, 2009, 2009 International Conference on Field-Programmable Technology.

Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design

Steven J. E. Wilton, Peter Y. K. Cheung, George A. Constantinides, 2009, 2009 International Conference on Field-Programmable Technology.

Congestion-driven regional re-clustering for low-cost FPGAs

Darius Chiu, Guy G.F. Lemieux, Steve Wilton, 2009, 2009 International Conference on Field-Programmable Technology.

Modeling post-techmapping and post-clustering FPGA circuit depth

Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton, 2009, 2009 International Conference on Field Programmable Logic and Applications.

An analytical model relating FPGA architecture and place and route runtime

Steven J. E. Wilton, Scott Y. L. Chin, S. Wilton, 2009, 2009 International Conference on Field Programmable Logic and Applications.

Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces

Steven J. E. Wilton, Bradley R. Quinton, S. Wilton, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Wirelength modeling for homogeneous and heterogeneous FPGA architectural development

Steven J. E. Wilton, Alastair M. Smith, Joydip Das, 2009, FPGA '09.

Optimizing coarse-grained units in floating point hybrid FPGA

Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton, 2008, 2008 International Conference on Field-Programmable Technology.

A system-level stochastic circuit generator for FPGA architecture evaluation

Steven J. E. Wilton, Cindy Mark, Ava Shui, 2008, 2008 International Conference on Field-Programmable Technology.

GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering

Guy Lemieux, Steven J. E. Wilton, Julien Lamoureux, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On the trade-off between power and flexibility of FPGA clock networks

Steven J. E. Wilton, Julien Lamoureux, S. Wilton, 2008, TRETS.

The Coarse-Grained / Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

Wayne Luk, Chi Wai Yu, Steven J.E. Wilton, 2008, 2008 4th Southern Conference on Programmable Logic.

Memory Footprint Reduction for FPGA Routing Algorithms

Steven J. E. Wilton, Scott Y. L. Chin, S. Wilton, 2007, 2007 International Conference on Field-Programmable Technology.

Embedded Programmable Logic Core Enhancements for System Bus Interfaces

Steven J. E. Wilton, Bradley R. Quinton, S. Wilton, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Clock-Aware Placement for FPGAs

Steven J. E. Wilton, Julien Lamoureux, S. Wilton, 2007, 2007 International Conference on Field Programmable Logic and Applications.

GlitchLess: an active glitch minimization technique for FPGAs

Guy Lemieux, Steven J. E. Wilton, Julien Lamoureux, 2007, FPGA '07.

Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs

Steven J. E. Wilton, Nathalie Chan King Choy, S. Wilton, 2006, 2006 IEEE International Conference on Field Programmable Technology.

Architecture and CAD for FPGA Clock Networks

Steven J. E. Wilton, Julien Lamoureux, S. Wilton, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays

Steven J. E. Wilton, Scott Y. L. Chin, Clarence S. P. Lee, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Routing architecture optimizations for high-density embedded programmable IP cores

Steven J. E. Wilton, Peter Hallschmid, S. Wilton, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Placement and routing for non-rectangular embedded programmable logic cores in SoC design

Steven J. E. Wilton, Tony Wong, S. Wilton, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

Architectures and algorithms for synthesizable embedded programmable logic cores

S. Wilton, Noha Kafafi, Kimberly A. Bozman, 2003, FPGA '03.

Programmable logic IP cores in SoC design: opportunities and challenges

Steven J. E. Wilton, Resve Saleh, S. Wilton, 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

A crosstalk-aware timing-driven router for FPGAs

Steven J. E. Wilton, S. Wilton, 2001, FPGA '01.

Detailed routing architectures for embedded programmable logic IP cores

Steven J. E. Wilton, Peter Hallschmid, S. Wilton, 2001, FPGA '01.

Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms

Steven J. E. Wilton, Scott Y. L. Chin, S. Wilton, 2009, TRETS.

MODELING THE RELATIONSHIP BETWEEN FPGA ARCHITECTURE AND PLACE AND ROUTE RUNTIME

Scott Y. L. Chin, S. Wilton, 2009 .

Online Training from Streaming Data with Concept Drift on FPGAs

S. Wilton, Esther Roorda, 2023, 2023 24th International Symposium on Quality Electronic Design (ISQED).