R. Bajwa

In-datacenter performance analysis of a tensor processing unit

David A. Patterson, Norman P. Jouppi, Kyle Lucke, 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

In-Datacenter Performance Analysis of a Tensor Processing UnitTM

Wang, Liu, Kyle A. Lucke, .

The MGAP's programming environment and the *C++ language

Mary Jane Irwin, Robert Michael Owens, Raminder Singh Bajwa, 1995, Proceedings The International Conference on Application Specific Array Processors.

Image processing with the MGAP: a cost effective solution

Mary Jane Irwin, Robert Michael Owens, Raminder Singh Bajwa, 1993, [1993] Proceedings Seventh International Parallel Processing Symposium.

Instruction buffering to reduce power in processors for signal processing

Raminder Singh Bajwa, Mitsuru Hiraki, Koichi Seki, 1997, IEEE Trans. Very Large Scale Integr. Syst..

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

Raminder Singh Bajwa, Mitsuru Hiraki, Koichi Seki, 1996, Proceedings / International Symposium on Low Power Electronics and Design.

Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP

H. Kojima, R. S. Bajwa, N. Schumann, 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.