S. Dasgupta

发表

Introduction to Nanoelectronics

B. Kaushik, S. Dasgupta, P. Pal, 2017 .

Analytical Modeling of DG-MOSFET in Subthreshold Regime by Green’s Function Approach

S. Dasgupta, Nilesh Pandey, Ashutosh Nandi, 2017, IEEE Transactions on Electron Devices.

Analytical Modeling of a Double Gate MOSFET Considering Source/Drain Lateral Gaussian Doping Profile

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2013, IEEE Transactions on Electron Devices.

Impact of series resistance on Si nanowire MOSFET performance

S. K. Manhas, Sudeb Dasgupta, Gaurav Kaushal, 2013 .

Modeling source/drain lateral Gaussian doping profile of DG-MOSFET using Green’s function approach

S. Dasgupta, Ashutosh Nandi, A. Shukla, 2020 .

Low band-to-band tunnelling and gate tunnelling current in novel nanoscale double-gate architecture: simulations and investigation

S. Dasgupta, D. Datta, S. Ganguly, 2007 .

Novel nanoscale device architecture to reduce leakage currents in logic circuits: a quantum-mechanical study

S. Dasgupta, D. Datta, S. Ganguly, 2006 .

Nanoscale device architecture to reduce leakage currents through quantum-mechanical simulation

S. Dasgupta, D. Datta, A. Sarab, 2006 .

Demonstration of a Novel Two Source Region Tunnel FET

S. Dasgupta, N. Bagga, Anil Kumar, 2017, IEEE Transactions on Electron Devices.

Analysis of propagation delay in mixed carbon nanotube bundle as global VLSI interconnects

Brajesh Kumar Kaushik, B. Kaushik, S. Dasgupta, 2012, 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics.

Modeling of threshold voltage, mobility, drain current and subthreshold leakage current in virgin and irradiated silicon-on-insulator fin-shaped field effect transistor device

Sudeb Dasgupta, S. S. Rathod, Ashok K. Saxena, 2011 .

Quantum mechanical analytical modeling of nanoscale DG FinFET: evaluation of potential, threshold voltage and source/ drain resistance

S. Dasgupta, B. Raj, A. Saxena, 2013 .

Insights into channel potentials and electron quasi-Fermi potentials for DG tunnel FETs

S. Dasgupta, A. Bulusu, Menka, 2015 .

Optimization of Design Parameters in Dual- $\kappa $ Spacer-Based Nanoscale Reconfigurable FET for Improved Performance

Sudeb Dasgupta, Abhishek Bhattacharjee, S. Dasgupta, 2016, IEEE Transactions on Electron Devices.

A Compact Physics-Based Surface Potential and Drain Current Model for an S/D Spacer-Based DG-RFET

S. Dasgupta, A. Bhattacharjee, 2018, IEEE Transactions on Electron Devices.

Analytical Modeling of Nanoscale Double Gate FinFET Device

S. Dasgupta, B. Raj, S. Vishvakarma, 2007 .

A review on the compact modeling of parasitic capacitance: from basic to advanced FETs

S. Dasgupta, M. Kartikeyan, S. Sharma, 2020, Journal of Computational Electronics.

A transformed analytical model for thermal noise of FinFET based on fringing field approximation

S. Dasgupta, S. Sharma, M. V. Kartikeyant, 2016 .

Mixed mode simulation of heavy ion impact on 3D SRAM cell

S. Dasgupta, A. Saxena, S. Rathod, 2009, 2009 4th International Conference on Computers and Devices for Communication (CODEC).

Drive matching issues in multi gate CMOS inverter

S. Dasgupta, S. Manhas, S. Maheshwaram, 2013, 2013 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATION (ICSC).

Analytical Potential Distribution Model for Underlap Double Gate MOSFETs with 3T-4T and Symmetric- Asymmetric Options for Subthreshold operation: A Conformal Mapping Approach

Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal, 2010 .

Statistical Variability and Sensitivity Analysis

B. Kaushik, S. Dasgupta, P. Pal, 2017 .

Design and Simulation of CNT Based Nano-Transistor for Greenhouse Gas Detection

S. K. Manhas, Sudeb Dasgupta, C. Venkataiah, 2018 .

Spacer Engineering-Based High-Performance Reconfigurable FET With Low OFF Current Characteristics

B. Anand, S. Dasgupta, S. Dasgupta, 2015, IEEE Electron Device Letters.

Source/Drain (S/D) Spacer-Based Reconfigurable Devices-Advantages in High-Temperature Applications and Digital Logic

S. Dasgupta, A. Bhattacharjee, 2020 .

Demonstration of a Novel Ferroelectric-Dielectric Negative Capacitance Tunnel FET

S. Dasgupta, N. Bagga, A. Bulusu, 2019, 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India).

A First Insight to the Thermal Dependence of the DC, Analog and RF Performance of an S/D Spacer Engineered DG-Ambipolar FET

S. Dasgupta, M. Saikiran, A. Bhattacharjee, 2017, IEEE Transactions on Electron Devices.

Performance Evaluation of a Novel GAA Schottky Junction (GAASJ) TFET with Heavily Doped Pocket

S. Dasgupta, Anil Kumar, N. Bagga, 2017 .

Effect of Border Traps on Electron Mobility of Nano-Scale MOS Devices

S. Dasgupta, A. Saxena, S. Rathod, 2010, 2010 International Symposium on Electronic System Design.

A Novel ${{V}}_{\textsf {DSAT}}$ Extraction Method for Tunnel FETs and Its Implication on Analog Design

S. Dasgupta, B. Anand, Abhishek Acharya, 2017, IEEE Transactions on Electron Devices.

A review on the compact modeling of parasitic capacitance: from basic to advanced FETs

M. V. Kartikeyan, S. Dasgupta, S. Sharma, 2020, Journal of Computational Electronics.

A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture

S. Dasgupta, B. Anand, A. Joshi, 2022, 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing

S. Dasgupta, R. Joshi, B. Anand, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS).

Energy estimation for n-input Adiabatic Logic gate: a Proposed Analytical Model

S. Dasgupta, Jitendra Kanungo, S. Dasgupta, 2013, J. Circuits Syst. Comput..

Efficient implementation of LMS adaptive filter-based FECG extraction on an FPGA

S. Dasgupta, Bhavya Vasudeva, Puneesh Deora, 2019, Healthcare technology letters.

FPGA Implementation of Efficient Series and Parallel Architectures for LMS Adaptive Filter based FECG Extraction

P. M. Pradhan, S. Dasgupta, Bhavya Vasudeva, 2019 .

Radiation Effects in MOS-based Devices and Circuits: A Review

Sudeb Dasgupta, S. S. Rathod, Ashok K. Saxena, 2011 .

FinFETs for RF Applications: A Literature review

S. Dasgupta, M. V. Kartikeyan, Savitesh M. Sharma, 2018, 2018 Conference on Emerging Devices and Smart Systems (ICEDSS).

Novel Design Methodology Using $L_{\bf EXT}$ Sizing in Nanowire CMOS Logic

Bulusu Anand, S. K. Manhas, Sudeb Dasgupta, 2014, IEEE Transactions on Nanotechnology.

Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design

Tony Tae-Hyoung Kim, Sudeb Dasgupta, R. P. Agarwal, 2011 .

Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic

Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal, 2010, Microelectron. J..

Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs

Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal, 2010, J. Low Power Electron..

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options

Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal, 2011, Microelectron. J..

Compact Modeling of a Generic Double-Gate MOSFET With Gate–S/D Underlap for Subthreshold Operation

S. Dasgupta, R. P. Agarwal, R. P. Agarwal, 2012, IEEE Transactions on Electron Devices.

Compact Analytical Model to Extract Write Static Noise Margin (WSNM) for SRAM Cell at 45-nm and 65-nm Nodes

Sudeb Dasgupta, . Ruchi, S. Dasgupta, 2018, IEEE Transactions on Semiconductor Manufacturing.

Gate-Pitch Optimization for Circuit Design Using Strain-Engineered Multifinger Gate Structures

B. Anand, S. Dasgupta, N. Alam, 2012, IEEE Transactions on Electron Devices.

Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation

Sudeb Dasgupta, Ashok K. Saxena, Surendra S. Rathod, 2011, Microelectron. J..

Super-threshold semi analytical channel potential model for DG tunnel FET

S. Dasgupta, A. Bulusu, M. Yadav, 2015 .

Super-threshold semi analytical channel potential model for DG tunnel FET

S. Dasgupta, A. Bulusu, M. Yadav, 2015, Journal of Computational Electronics.

Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field

Bulusu Anand, Sudeb Dasgupta, Menka Yadav, 2013, Microelectron. J..

A TCAD approach to evaluate channel electron density of double gate symmetric n-tunnel FET

S. Dasgupta, B. Anand, Menka, 2012, 2012 Annual IEEE India Conference (INDICON).

Tuning Source/Drain Extension Profile for Current Matching in Nanowire CMOS Logic

B. Anand, S. Dasgupta, S. K. Manhas, 2012, IEEE Transactions on Nanotechnology.

Study of Self Heating Effect in the wake of complete and partial bottom dielectric insertion under 5 nm Stacked Nanosheet Transistor

S. Dasgupta, Arnab Datta, Jyoti Patel, 2023, Memories - Materials, Devices, Circuits and Systems.

Surface Potential and Drain Current Analytical Model of Gate All Around Triple Metal TFET

Sudeb Dasgupta, Navjeet Bagga, S. Dasgupta, 2017, IEEE Transactions on Electron Devices.

Modeling of Leakage Current Mechanisms in Nanoscale DG MOSFET and its Application to Low Power SRAM Design

Sudeb Dasgupta, Deblina Sarkar, Deepanjan Datta, 2008, J. Comput..

Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design

Sudeb Dasgupta, Samiran Ganguly, Deblina Sarkar, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier

Sudeb Dasgupta, Ashok K. Saxena, Surendra S. Rathod, 2011, Microelectron. Reliab..

Investigation of Symmetric Dual- $k$ Spacer Trigate FinFETs From Delay Perspective

Brajesh Kumar Kaushik, Sudeb Dasgupta, Pankaj Kumar Pal, 2014, IEEE Transactions on Electron Devices.

High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications

Brajesh Kumar Kaushik, Pankaj Kumar Pal, S. Dasgupta, 2014, 18th International Symposium on VLSI Design and Test.

Two dimensional analytical subthreshold swing model of a double gate MOSFET with Gate-S/D underlap, asymmetric and independent gate features

R. P. Agarwal, S. Dasgupta, R. Vaddi, 2011, 2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA).

Enhanced device performance using lightly doped channel junctionless accumulation-mode FinFET

B. Kaushik, S. Dasgupta, P. Pal, 2015, 2015 12th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON).

Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-polar Gases

Neeraj Jain, S. K. Manhas, Sudeb Dasgupta, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

FPGA: An Efficient And Promising Platform For Real-Time Image Processing Applications

Sparsh Mittal, Sudeb Dasgupta, Saket Gupta, 2014 .

Analysis and Modeling of Leakage Currents in Stacked Gate-All-Around Nanosheet Transistors

S. Dasgupta, N. Bagga, Sourajeet Roy, 2022, 2022 IEEE International Conference on Emerging Electronics (ICEE).

A proposed DG-FinFET based SRAM cell design with RadHard capabilities

Sudeb Dasgupta, Ashok K. Saxena, Surendra S. Rathod, 2010, Microelectron. Reliab..

High-Performance and Robust SRAM Cell Based on Asymmetric Dual-$k$ Spacer FinFETs

Brajesh Kumar Kaushik, Sudeb Dasgupta, Pankaj Kumar Pal, 2013, IEEE Transactions on Electron Devices.

Analytical modeling for the estimation of leakage current and subthreshold swing factor of nanoscale double gate FinFET device

Balwinder Raj, Sudeb Dasgupta, Ashok K. Saxena, 2009 .

Ab-initio Multiscale Thermal Modeling of 5 nm Stacked Nanosheet Field Effect Transistor for Thermal Hotspot Optimization inside the Channel

S. Dasgupta, Arnab Datta, Vivek Kumar, 2023, 2023 22nd IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).

Multifinger MOSFETs’ Optimization Considering Stress and INWE in Static CMOS Circuits

Sudeb Dasgupta, Naushad Alam, Anand Bulusu, 2016, IEEE Transactions on Electron Devices.

Recent trend of FinFET devices and its challenges: A review

S. Dasgupta, Ravi Shankar Pal, Savitesh Sharma, 2017, 2017 Conference on Emerging Devices and Smart Systems (ICEDSS).

An Improved Analytical Model of Outer Fringe Capacitance of Multifin Diamond Shaped Raised Source/Drain FinFET

S. Dasgupta, M. Kartikeyan, S. Sharma, 2020, Silicon.

Successive Conformal Mapping Technique to Extract Inner Fringe Capacitance of Underlap DG-FinFET and Its Variations With Geometrical Parameters

M. V. Kartikeyan, Sudeb Dasgupta, Savitesh Madhulika Sharma, 2017, IEEE Transactions on Electron Devices.

Design and Analysis of Analog Performance of Dual-k Spacer Underlap N/P-FinFET at 12 nm Gate Length

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2013, IEEE Transactions on Electron Devices.

Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach

Balwinder Raj, Sudeb Dasgupta, Ashok K. Saxena, 2010, 2010 Fourth UKSim European Symposium on Computer Modeling and Simulation.

Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance

Bulusu Anand, Sudeb Dasgupta, Naushad Alam, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Comparison of nano-scale complementary metal-oxide semiconductor and 3T-4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic

Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal, 2010, IET Circuits Devices Syst..

Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances

Bulusu Anand, Archana Pandey, Sudeb Dasgupta, 2014, IEEE Transactions on Electron Devices.

Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric

Khoirom Johnson Singh, Lomash Chandra Acharya, S. Dasgupta, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS).

Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis

Brajesh Kumar Kaushik, Sudeb Dasgupta, Pankaj Kumar Pal, 2015, IEEE Transactions on Electron Devices.

Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients

Sudeb Dasgupta, Ashok K. Saxena, Surendra S. Rathod, 2012, IET Circuits Devices Syst..

Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective

S. Dasgupta, B. Anand, Abhishek Acharya, 2018, IEEE Transactions on Electron Devices.

Demonstration of a novel tunnel FET with channel sandwiched by drain

S. Dasgupta, N. Bagga, Shashank Banchhor, 2019, Semiconductor Science and Technology.

Low power SRAM design for 14 nm GAA Si-nanowire technology

S. K. Manhas, Sudeb Dasgupta, Gaurav Kaushal, 2015, Microelectron. J..

Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET

Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Investigation of robustness and performance comparisons of 3T - 4T DG-FinFETs for ultra low power subthreshold logic

Ramesh Vaddi, S. Dasgupta, R. P. Agarwal, 2009, 2009 4th International Conference on Computers and Devices for Communication (CODEC).

SDG vs ADG with tied and independent gate options in the subthreshold logic for ultra low power applications

Ramesh Vaddi, S. Dasgupta, R. P. Agarwal, 2009, 2009 2nd International Workshop on Electron Devices and Semiconductor Technology.

Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET

Sudeb Dasgupta, Deepanjan Datta, A. Ananda Prasad Sarab, 2006, Microelectron. J..

Efficient static D-latch standard cell characterization using a novel setup time model

Bulusu Anand, Sudeb Dasgupta, Yogendra Sharma, 2015, Sixteenth International Symposium on Quality Electronic Design.

A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits

Brajesh Kumar Kaushik, Surabhi Singh, Sudeb Dasgupta, 2013, VDAT.

Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers

Brajesh Kumar Kaushik, Sudeb Dasgupta, Pankaj Kr. Pal, 2013, VDAT.

A review of Analytical thermal noise model

S. Dasgupta, M. V. Kartikeyan, Savitesh Madhulika Sharma, 2016, 2016 Conference on Emerging Devices and Smart Systems (ICEDSS).

Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm

S. Dasgupta, B. Anand, Surinder Singh, 2023, 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID).

A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application

S. Dasgupta, R. Joshi, B. Anand, 2023, 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS).