E. Nowak

发表

Channel electron mobility dependence on lateral electric field in field-effect transistors

D. Hoyniak, E. Nowak, R. Anderson, 2000 .

Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation

Kok Wai Wong, E. Nowak, D. Boyd, 2002, Digest. International Electron Devices Meeting,.

Scaling planar silicon devices

Ching-Te Chuang, E. Nowak, K. Kim, 2004, IEEE Circuits and Devices Magazine.

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

D. Lea, E. Nowak, S. Yang, 2003, IEEE International Electron Devices Meeting 2003.

High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

E. Nowak, D. Frank, W. Haensch, 2006 .

Nonlinear characteristics of Weibull breakdown distributions and its impact on reliability projection for ultra-thin oxides

E. Nowak, W. Abadeer, E. Wu, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Weibull breakdown characteristics and oxide thickness uniformity

E. Nowak, E. Wu, L. Han, 2000 .

The effective drive current in CMOS inverters

E.J. Nowak, W. Haensch, M.H. Na, 2002, Digest. International Electron Devices Meeting,.

RF Potential of a 0 . 18-m CMOS Logic Device Technology

M. Hargrove, E. Nowak, K. Jenkins, 2000 .

RF potential of a 0.18-/spl mu/m CMOS logic device technology

M. Hargrove, E. Nowak, K. Jenkins, 2000 .

High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices

E. Nowak, D. Boyd, J. Kedzierski, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Silicon CMOS devices beyond scaling

Arvind Kumar, Robert H. Dennard, Paul M. Solomon, 2006, IBM J. Res. Dev..

Low-power CMOS at Vdd = 4kT/q

E. Nowak, P. Cottrell, J. Brown, 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).

Optimization of boron pocket implantation for deep sub-micron NMOSFET process

E. Nowak, Chun Jiang, L. Ding, 1995, Proceedings of 4th International Conference on Solid-State and IC Technology.

Structural dependence of dielectric breakdown in ultra-thin gate oxides and its relationship to soft breakdown modes and device failure

W. Abadeer, E. Nowak, J. Aitken, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

RF potential of a 0.18-/spl mu/m CMOS logic technology

R. Logan, E. Nowak, K. Jenkins, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Self-Consistent and Efficient Electro-Thermal Analysis for Poly/Metal Gate FinFETs

Ching-Te Chuang, Keunwoo Kim, E. Nowak, 2006, 2006 International Electron Devices Meeting.

A Fin-type independent-double-gate NFET

J. Kedzierski, E. Nowak, J. Kedzierski, 2003, 61st Device Research Conference. Conference Digest (Cat. No.03TH8663).

A sub 40-nm body thickness n-type FinFET

A.P. Johnson, E. Nowak, D. Fried, 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).

A functional FinFET-DGCMOS SRAM cell

J. Kedzierski, M. Breitwisch, M. Breitwisch, 2002, Digest. International Electron Devices Meeting,.

Demonstration of FinFET CMOS circuits

J. Kedzierski, E. Nowak, J. Kedzierski, 2002, 60th DRC. Conference Digest Device Research Conference.

FinFET SRAM for high-performance low-power applications

I. Aller, T. Ludwig, E. Nowak, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

Off-state mode TDDB reliability for ultra-thin gate oxides: New methodology and the impact of oxide thickness scaling

E. Nowak, E. Wu, W. Lai, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

Modeling and Characterization of Gate Leakage in High-K Metal Gate Technology-Based Embedded DRAM

E. Nowak, S. Furkay, S. Iyer, 2013, IEEE Transactions on Electron Devices.

Crystallographic-Orientation-Dependent Gate-Induced Drain Leakage in Nanoscale MOSFETs

E. Nowak, S. Furkay, K. Murali, 2010, IEEE Transactions on Electron Devices.

A 0.18 /spl mu/m high-performance logic technology

S. Greco, M. Hargrove, X. Chen, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

CMOS scaling into the 21st century: 0.1 µm and beyond

Yuan Taur, H.-S. Philip Wong, David J. Frank, 1995, IBM J. Res. Dev..

Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures

E. Nowak, P. Zeitzoff, A. Razavieh, 2019, IEEE Transactions on Nanotechnology.

Titanium silicide/silicon nonohmic contact resistance for NFET's, PFET's, diffused resistors, and NPN's in a BiCMOS technology

E. Nowak, R. Mann, T. Hook, 1995 .

The Impact of Width Granularity on FinFET Latch Operation and Optimization

Huifang Qin, Thomas Ludwig, Jan Rabaey, 2004 .

Device scaling limits of Si MOSFETs and their application dependencies

Yuan Taur, David J. Frank, Robert H. Dennard, 2001, Proc. IEEE.

Turning silicon on its edge [double gate CMOS/FinFET technology]

E.J. Nowak, I. Aller, T. Ludwig, 2004, IEEE Circuits and Devices Magazine.

Overview of gate linewidth control in the manufacture of CMOS logic chips

D. G. Chesebro, J. W. Adkisson, L. R. Clark, 1995, IBM J. Res. Dev..

A CMOS Technology for a Sub-5-ns 3.3-V LVTTL 1-Mbit SRAM

E. Nowak, K. Watson, T. Hook, 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.

Voltage-splitting technique for reliability evaluation of off-state mode of MOSFETs in ultrathin gate oxides

E. Nowak, E. Nowak, E. Wu, 2004, IEEE Electron Device Letters.

Experimental evidence of T/sub BD/ power-law for voltage dependence of oxide breakdown in ultrathin gate oxides

Jordi Suñé, Ernest Y. Wu, Edward J. Nowak, 2002 .

High Performance CMOS Variability in the 65nm Regime and Beyond

Sani R. Nassif, Edward J. Nowak, Wilfried Haensch, 2006, 2007 IEEE International Electron Devices Meeting.

Scaling challenges of FinFET architecture below 40nm contacted gate pitch

E. Nowak, G. Karve, D. Brown, 2017, 2017 75th Annual Device Research Conference (DRC).

CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics

Edward J. Nowak, Ernest Y. Wu, Wing L. Lai, 2002, IBM J. Res. Dev..

Maintaining the benefits of CMOS scaling when scaling bogs down

Edward J. Nowak, E. Nowak, 2002, IBM J. Res. Dev..

New global insight in ultrathin oxide reliability using accurate experimental methodology and comprehensive database

Ernest Y. Wu, Edward J. Nowak, A. Vayshenker, 2001 .

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A high-performance 0.08 /spl mu/m CMOS

E. Nowak, A. Ray, P. Agnello, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Status and Direction of Communication Technologies - SiGe BiCMOS and RFCMOS

James S. Dunn, Edward J. Nowak, Alvin J. Joseph, 2005, Proceedings of the IEEE.

Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology

L. Liebmann, Y. M. Lee, M. H. Na, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

FinFET technology for future microprocessors

T. Ludwig, I. Aller, V. Gernhoefer, 2003, 2003 IEEE International Conference on SOI.

Scaling beyond the 65 nm node with FinFET-DGCMOS

Joachim Keinert, David M. Fried, Matthew J. Breitwisch, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

Critical reliability challenges in scaling SiO2-based dielectric to its limit

Jordi Suñé, Edward J. Nowak, Ernest Y. Wu, 2003, Microelectron. Reliab..

Extension and source/drain design for high-performance FinFET devices

Ying Zhang, David M. Fried, Meikei Ieong, 2003 .