J. David

J. M. Pierre Langlois, Jean-Pierre David, Sivakumar Chidambaram, 2018, 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP).

SHard: a Scheme to Hardware Compiler

Marc Feeley, Xavier Saint-Mleux, Jean-Pierre David, 2006 .

A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters

Jean-Pierre David, Tarek Ould Bachir, Hugo Fortin-Blanchette, 2012, IEEE Transactions on Industrial Electronics.

High level synthesis for data-driven applications

Marc Feeley, Etienne Bergeron, Xavier Saint-Mleux, 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).

A Low-Latency Reconfigurable Multistage Interconnection Network

Jean-Pierre David, Tarek Ould Bachir, Jean Mahseredjian, 2019, 2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE).

PoET-BiN: Power Efficient Tiny Binary Neurons pdf

J. M. Pierre Langlois, Sivakumar Chidambaram, Jean Pierre David, 2020, MLSys.

Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation

Marc Feeley, Etienne Bergeron, Jean-Pierre David, 2011, TRETS.

Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs

Marc Feeley, Etienne Bergeron, Jean-Pierre David, 2008, CC.

Ultra-low latency communication channels for FPGA-based HPC cluster

Jean-Pierre David, Roberto Sanchez Correa, J. David, 2018, Integr..

Effective FPGA-based electric motor modeling with floating-point cores

Christian Dufour, Jean Belanger, Jean-Pierre David, 2010, IECON 2010 - 36th Annual Conference on IEEE Industrial Electronics Society.

FPGA-based real-time simulation of state-space models using floating-point cores

Jean-Pierre David, Tarek Ould Bachir, J. David, 2010, Proceedings of 14th International Power Electronics and Motion Control Conference EPE-PEMC 2010.

Automated Synthesis of Streaming Transfer Level Hardware Designs

Jean-Pierre David, Marc-André Daigneault, J. David, 2018, ACM Trans. Reconfigurable Technol. Syst..

POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA

Ahmed M. Abdelsalam, J. M. Pierre Langlois, Ahmed Elsheikh, 2018, 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP).

An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters

Jean Pierre David, Tarek Ould-Bachir, Federico Montano, 2018, IEEE Transactions on Industrial Electronics.

Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators

Jean-Pierre David, Tarek Ould Bachir, J. David, 2013, TRETS.

POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees

Ahmed M. Abdelsalam, J. M. Pierre Langlois, Ahmed Elsheikh, 2020, J. Signal Process. Syst..

Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries.

J. David, Y. Savaria, Dufour Jules, 2023, 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS).

U-Net Fixed-Point Quantization for Medical Image Segmentation

Christian S. Perone, Julien Cohen-Adad, Yvon Savaria, 2019, LABELS/HAL-MICCAI/CuRIOUS@MICCAI.

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

Jean-Pierre David, Tarek Ould-Bachir, Federico Montano, 2020, Electronics.

Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only)

Jean-Pierre David, Marc-André Daigneault, J. David, 2010, FPGA '10.

Binary Speech Features for Keyword Spotting Tasks

Jean-Pierre David, Alexandre Riviello, J. David, 2019, INTERSPEECH.

A Multi-FPGA System for Prototyping Power Conscious Algorithms

Jean-Didier Legat, Jean-Pierre David, Ricardo Ferreira, 2000 .