J. Kavalieros

发表

Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

G. Dewey, B. Chu-Kung, J. Boardman, 2011, 2011 International Electron Devices Meeting.

High performance fully-depleted tri-gate CMOS transistors

J. Kavalieros, R. Chau, B. Doyle, 2003, IEEE Electron Device Letters.

Gate dielectric scaling for high-performance CMOS: from SiO2 to high-K

J. Kavalieros, M. Metz, R. Chau, 2003, Extended Abstracts of International Workshop on Gate Insulator (IEEE Cat. No.03EX765).

BTI reliability of 45 nm high-K + metal-gate process technology

G. Dewey, J. Kavalieros, M. Metz, 2008, 2008 IEEE International Reliability Physics Symposium.

100 nm gate length high performance/low power CMOS transistor structure

J. Kavalieros, C. Kenyon, R. Nagisetty, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Integrated nanoelectronics for the future.

J. Kavalieros, R. Chau, S. Datta, 2007, Nature materials.

30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

G. Dewey, J. Kavalieros, R. Chau, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation

G. Dewey, B. Chu-Kung, J. Boardman, 2011, 2011 International Electron Devices Meeting.

Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

G. Dewey, J. Kavalieros, M. Metz, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Advanced high-K gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications

G. Dewey, B. Chu-Kung, J. Fastenau, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture

G. Dewey, B. Chu-Kung, J. Kavalieros, 2010, 2010 International Electron Devices Meeting.

Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications

G. Dewey, B. Chu-Kung, J. Fastenau, 2010, 2010 International Electron Devices Meeting.

Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

G. Dewey, J. Kavalieros, M. Metz, 2005 .

Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET

G. Dewey, B. Chu-Kung, J. Kavalieros, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

High-/spl kappa//metal-gate stack and its MOSFET characteristics

J. Kavalieros, M. Metz, R. Chau, 2004, IEEE Electron Device Letters.

Direct-current measurements of oxide and interface traps on oxidized silicon

J. Kavalieros, T. Nishida, C. Sah, 1995 .

Advanced High-K Gate Dielectric for High-Performance Short-Channel In 0 . 7 Ga

G. Dewey, B. Chu-Kung, J. Fastenau, 2009 .

High- /Metal-Gate Stack and Its MOSFET Characteristics

Suman Datta, Brian S. Doyle, J. Kavalieros, 2004 .

ing Interface Traps in MOS Transistors

J. Kavalieros, C. Sah, K. M. Han, 1996 .

300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low Power High Performance Logic Applications

G. Dewey, B. Chu-Kung, J. Kavalieros, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

MOVPE III–V material growth on silicon substrates and its comparison to MBE for future high performance and low power logic applications

G. Dewey, B. Chu-Kung, J. Boardman, 2011, International Electron Devices Meeting.

A 50 nm depleted-substrate CMOS transistor (DST)

J. Kavalieros, B. Doyle, R. Chau, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application

J. Kavalieros, M. Metz, A. Murthy, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit

R.S. Chau, J. Kavalieros, R. Chau, 2000, IEEE Electron Device Letters.

Experimental observation and physics of “negative” capacitance and steeper than 40mV/decade subthreshold swing in Al0.83In0.17N/AlN/GaN MOS-HEMT on SiC substrate

J. Kavalieros, R. Chau, G. Dewey, 2013, 2013 IEEE International Electron Devices Meeting.

Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

S. Hareland, J. Kavalieros, B. Doyle, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling

G. Dewey, J. Kavalieros, M. Metz, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics

J. Kavalieros, B. Doyle, R. Chau, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Emerging silicon and nonsilicon nanoelectronic devices: opportunities and challenges for future high-performance and low-power computational applications

J. Kavalieros, B. Doyle, R. Chau, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Hafnia-Based FeRAM: A Path Toward Ultra-High Density for Next-Generation High-Speed Embedded Memory

Hai Helen Li, J. Kavalieros, M. Metz, 2022, 2022 International Electron Devices Meeting (IEDM).

FeRAM using Anti-ferroelectric Capacitors for High-speed and High-density Embedded Memory

J. Kavalieros, M. Metz, M. Radosavljevic, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack

S. Datta, J. Kavalieros, R. Chau, 2003, IEEE International Electron Devices Meeting 2003.

Opportunities in 3-D stacked CMOS transistors

G. Dewey, J. Kavalieros, M. Metz, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Heterogeneous integration of enhancement mode in0.7ga0.3as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications

S. Datta, J. Kavalieros, R. Chau, 2007, 2007 IEEE International Electron Devices Meeting.

Separation of interface and nonuniform oxide traps by the DC current-voltage method

Chih-Tang Sah, J. Kavalieros, C. Sah, 1996 .