A. Hikavyy

发表

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE Symposium on VLSI Technology.

Fabrication and Analysis of a ${\rm Si}/{\rm Si}_{0.55}{\rm Ge}_{0.45}$ Heterojunction Line Tunnel FET

A. Hikavyy, A. Thean, N. Collaert, 2014, IEEE Transactions on Electron Devices.

High performance Si.45Ge.55 Implant Free Quantum Well FET featuring low temperature process, eSiGe stressor and transversal strain relaxation

A. Hikavyy, H. Bender, N. Horiguchi, 2011, 2011 International Electron Devices Meeting.

Advancing CMOS beyond the Si roadmap with Ge and III/V devices

A. Hikavyy, C. Merckling, N. Waldron, 2011, 2011 International Electron Devices Meeting.

Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration

A. Hikavyy, G. Mannaert, T. Schram, 2011, 2011 International Electron Devices Meeting.

1mA/um-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D

A. Hikavyy, H. Dekkers, N. Horiguchi, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

A. Hikavyy, N. Collaert, M. Jurczak, 2007, 2007 IEEE Symposium on VLSI Technology.

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

A. Hikavyy, K. Devriendt, S. Demuynck, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth

Rita Rooyackers, Nadine Collaert, Malgorzata Jurczak, 2008 .

A new complementary hetero-junction vertical Tunnel-FET integration scheme

A. Hikavyy, K. Devriendt, A. Thean, 2013, 2013 IEEE International Electron Devices Meeting.

Gatestacks for scalable high-performance FinFETs

A. Hikavyy, N. Collaert, M. Jurczak, 2007, 2007 IEEE International Electron Devices Meeting.

First demonstration of monocrystalline silicon macaroni channel for 3-D NAND memory devices

A. Hikavyy, E. Rosseel, N. Jossart, 2018, 2018 IEEE Symposium on VLSI Technology.

Experimental and theoretical verification of channel conductivity degradation due to grain boundaries and defects in 3D NAND

A. Hikavyy, R. Degraeve, D. Linten, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling

W. Li, A. Vandooren, Liesbeth Witters, 2018, 2018 International Conference on IC Design & Technology (ICICDT).

Low-temperature pre-epitaxy surface cleaning of Si and SiGe

Roger Loo, Andriy Hikavyy, Sandeep Mehta, 2015 .

3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

F. M. Bufler, F. Inoue, R. Ritzenthaler, 2018, IEEE Transactions on Electron Devices.

Low‐Temperature Selective Growth of Heavily Boron‐Doped Germanium Source/Drain Layers for Advanced pMOS Devices

A. Hikavyy, E. Rosseel, B. Douhard, 2019, physica status solidi (a).

Processing Technologies for Advanced Ge Devices

Naoto Horiguchi, Jerome Mitard, Liesbeth Witters, 2017 .

Superior NBTI reliability of SiGe channel pMOSFETs: Replacement gate, FinFETs, and impact of Body Bias

A. Hikavyy, N. Horiguchi, L. Ragnarsson, 2011, 2011 International Electron Devices Meeting.

85nm-wide 1.5mA/µm-ION IFQW SiGe-pFET: Raised vs embedded Si0.75Ge0.25 S/D benchmarking and in-depth hole transport study

A. Hikavyy, N. Horiguchi, A. Thean, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Stress simulations for optimal mobility group IV p- and nMOS FinFETs for the 14 nm node and beyond

A. Hikavyy, A. De Keersgieter, O. Richard, 2012, 2012 International Electron Devices Meeting.

Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs

Rita Rooyackers, Anne Vandooren, Guido Groeseneken, 2013 .

First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

A. Hikavyy, K. Wostyn, H. Bender, 2018, IEEE Transactions on Electron Devices.

First demonstration of strained Ge-in-STI IFQW pFETs featuring raised SiGe75% S/D, replacement metal gate and germanided local interconnects

A. Hikavyy, H. Bender, A. Thean, 2013, 2013 Symposium on VLSI Circuits.

Challenges for introducing Ge and III/V devices into CMOS technologies

B. Kaczer, G. Hellings, L. Witters, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

TEM investigations of gate-all-around nanowire devices

H. Mertens, A. Hikavyy, O. Richard, 2019, Semiconductor Science and Technology.

Local Arrangement of Substitutional C Atoms and the Thermal Stability of Epitaxial Si:C(P) Grown by CVD

A. Hikavyy, E. Rosseel, R. Loo, 2017 .

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

L. Witters, N. Waldron, D. Mocuta, 2017, IEEE Transactions on Electron Devices.

On the manifestation of phosphorus-vacancy complexes in epitaxial Si:P films

A. Hikavyy, E. Rosseel, G. Pourtois, 2016 .

Si1-yGeyor Ge1-zSnzSource/Drain Stressors on Strained Si1-xGex-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

A. Hikavyy, N. Horiguchi, A. Thean, 2013 .

On the Evolution of Strain and Electrical Properties in As-Grown and Annealed Si: P Epitaxial Films for Source-Drain Stressor Applications

A. Hikavyy, E. Rosseel, G. Pourtois, 2018 .

High-Performance Si0.45Ge0.55 Implant-Free Quantum Well pFET With Enhanced Mobility by Low-Temperature Process and Transverse Strain Relaxation

Naoto Horiguchi, Geert Hellings, Jerome Mitard, 2014, IEEE Transactions on Electron Devices.

Review—Device Assessment of Electrically Active Defects in High-Mobility Materials

A. Hikavyy, C. Merckling, R. Loo, 2016 .

Influence of the process sequence and thermal budget on the strain of Si:C stressor layers formed by ion implantation

A. Hikavyy, E. Rosseel, T. Schram, 2010, 2010 18th International Conference on Advanced Thermal Processing of Semiconductors (RTP).

Stress Analysis and Junction Leakage of Sub-Melt Laser Annealed SiGe Epitaxial Layers

A. Hikavyy, E. Rosseel, R. Loo, 2010, IEEE Transactions on Semiconductor Manufacturing.

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

B. Parvais, A. Vandooren, G. Hellings, 2018, 2018 IEEE Symposium on VLSI Technology.

Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2021, 2021 Symposium on VLSI Technology.

Integration and Electrical Evaluation of Epitaxially Grown Si and SiGe Channels for Vertical NAND Memory Applications

A. Hikavyy, R. Degraeve, J. Lisoni, 2015, 2015 IEEE International Memory Workshop (IMW).

Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration

A. Hikavyy, E. Rosseel, B. Douhard, 2019, ECS Journal of Solid State Science and Technology.

Investigation of hydrogenated CVD diamond films by photo-thermal ionization spectroscopy

A. Hikavyy, K. Haenen, M. Nesladek, 2006 .

An In-depth Study of High-Performing Strained Germanium Nanowires pFETs

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2018, 2018 IEEE Symposium on VLSI Technology.

PTIS investigation of hydrogenated CVD diamond films

A. Hikavyy, K. Haenen, M. Nesladek, 2005 .

Dangling bond defects in silicon-passivated strained-Si1−xGex channel layers

A. Hikavyy, B. Kaczer, V. Afanas’ev, 2019, Journal of Materials Science: Materials in Electronics.

Low temperature epitaxial growth of Ge:B and Ge0.99Sn0.01:B source/drain for Ge pMOS devices: in-situ and conformal B-doping, selectivity towards oxide and nitride with no need for any post-epi activation treatment

A. Hikavyy, R. Loo, L. Witters, 2019, Japanese Journal of Applied Physics.

Insights into the C Distribution in Si:C/Si:C:P and the Annealing Behavior of Si:C Layers

A. Hikavyy, E. Rosseel, G. Pourtois, 2019, ECS Journal of Solid State Science and Technology.

Heterostructure at CMOS source/drain: Contributor or alleviator to the high access resistance problem?

A. Hikavyy, S. Chew, E. Rosseel, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

(Invited) Selective Etch of Si and SiGe for Gate All-Around Device Architecture

Naoto Horiguchi, Liesbeth Witters, Aaron Thean, 2015 .

Atomic layer deposition of ZnO thin films on boron-doped nanocrystalline diamond

J. Butler, A. Hikavyy, P. Visschere, 2007 .

Atomic layer deposition of ZnS thin films based on diethyl zinc and hydrogen sulfide

A. Hikavyy, K. Neyts, P. Visschere, 2002 .

Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits

A. Hikavyy, E. Rosseel, K. Devriendt, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG

A. Hikavyy, A. De Keersgieter, G. Mannaert, 2019, 2019 Symposium on VLSI Technology.

First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

A. Hikavyy, K. Wostyn, H. Bender, 2018, 2018 IEEE Symposium on VLSI Technology.

A 2nd Generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE Symposium on VLSI Technology.

Influence of precursor gas on SiGe epitaxial material quality in terms of structural and electrical defects

A. Hikavyy, R. Loo, E. Simoen, 2015 .

Group IV Epi processing, evolution in CMOS from 90 to 10nm node

Robert Langer, Roger Loo, Wei Wang, 2014 .

High depth resolution analysis of Si/SiGe multilayers with the atom probe

A. Hikavyy, O. Richard, W. Vandervorst, 2009 .

Use of high order precursors for manufacturing gate all around devices

Naoto Horiguchi, Liesbeth Witters, Andriy Hikavyy, 2017 .

Application Of HCl Gas Phase Etch In The Production Of Novel Devices

A. Hikavyy, R. Loo, R. Rooyackers, 2008 .

Impact of sub-melt laser annealing on Si1-xGex source /drain defectivity

A. Hikavyy, E. Rosseel, O. Richard, 2007, 2007 15th International Conference on Advanced Thermal Processing of Semiconductors.

High-mobility 0.85nm-EOT Si0.45Ge0.55-pFETs: Delivering high performance at scaled VDD

A. Mercha, L. Witters, J. Mitard, 2010, 2010 International Electron Devices Meeting.

Compressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors

A. Hikavyy, B. Douhard, O. Richard, 2014 .

15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

A. Brand, P. Eyben, L. Witters, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

In-Line Characterization of Heterojunction Bipolar Transistor Base Layers by High-Resolution X-Ray Diffraction

A. Hikavyy, R. Loo, N. D. Nguyen, 2007 .

Characterization of Highly Doped Si:P, Si:As and Si:P:As Epi Layers for Source/Drain Epitaxy

A. Hikavyy, E. Rosseel, B. Douhard, 2019, ECS Transactions.

A. Hikavyy, E. Rosseel, R. Loo, 2017 .

Chemical vapor deposition of Si:C and Si:C:P films—Evaluation of material quality as a function of C content, carrier gas and doping

A. Hikavyy, E. Rosseel, O. Richard, 2015 .

Characterization of Epitaxial Si:C:P and Si:P Layers for Source/Drain Formation in Advanced Bulk FinFETs

A. Hikavyy, K. Wostyn, G. Mannaert, 2014 .

Stress Techniques and Mobility Enhancement in FinFET Architectures

Naoto Horiguchi, Geert Hellings, Anabela Veloso, 2013 .

Ultralow resistive wrap around contact to scaled FinFET devices by using ALD-Ti contact metal

A. Hikavyy, S. Chew, G. Mannaert, 2017, 2017 IEEE International Interconnect Technology Conference (IITC).

Standard cell level parasitics assessment in 20nm BPL and 14nm BFF

A. Mercha, D. Verkest, M. Badaroglu, 2012, International Electron Devices Meeting.

Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation

A. Hikavyy, S. Chew, E. Rosseel, 2016, 2016 IEEE Symposium on VLSI Technology.

High Ge Content SiGe Selective Processes for Source/Drain in Manufacturing the Next Generations of pMOS Transistors

A. Hikavyy, R. Loo, L. Witters, 2013 .

Growth of high Ge content SiGe on (110) oriented Si wafers

A. Hikavyy, H. Bender, R. Loo, 2012 .

Contact Resistivity of Highly Doped Si:P, Si:As, and Si:P:As Epi Layers for Source/Drain Epitaxy

A. Hikavyy, E. Rosseel, B. Douhard, 2020, ECS Meeting Abstracts.

Ge-Source Vertical Tunnel FETs Using a Novel Replacement-Source Integration Scheme

A. Hikavyy, K. Devriendt, A. Thean, 2014, IEEE Transactions on Electron Devices.

An investigation of structural and electrical properties of boron doped and undoped nanocrystalline diamond films

J. Butler, A. Hikavyy, K. Haenen, 2006 .

Phosphorus doped SiC Source Drain and SiGe channel for scaled bulk FinFETs

R. Ritzenthaler, A. Hikavyy, G. Mannaert, 2012, 2012 International Electron Devices Meeting.

Quantitative depth profiling of SiGe‐multilayers with the Atom Probe

A. Hikavyy, O. Richard, W. Vandervorst, 2011 .

Small target compatible dimensional and analytical metrology for semiconductor nanostructures using x-ray fluorescence techniques

A. Hikavyy, A. Veloso, R. Loo, 2023, Advanced Lithography.

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

B. Parvais, A. Vandooren, J. Ryckaert, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

(Invited) High Ge Content SiGe Thin Films: Growth, Properties and Integration

H. Mertens, A. Hikavyy, E. Rosseel, 2014 .

Low Temperature Pre-Epi Treatment: Critical Parameters to Control Interface Contamination

A. Hikavyy, R. Loo, M. Caymax, 2009 .

Low temperature epitaxy and the importance of moisture control

A. Hikavyy, R. Loo, M. Caymax, 2008 .

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

A. Jourdain, G. Beyer, E. Beyne, 2020, ECS Journal of Solid State Science and Technology.

Low Temperature SiGe Steam Oxide - Aqueous Hf and NH3/NF3 Remote Plasma Etching and its Implementation as Si GAA Inner Spacer

H. Mertens, A. Hikavyy, K. Wostyn, 2018, Solid State Phenomena.

Study of electrically active defects in epitaxial layers on silicon

A. Hikavyy, K. Barla, R. Loo, 2016, 2016 China Semiconductor Technology International Conference (CSTIC).

Properties and growth peculiarities of Si0.30Ge0.70 stressor integrated in 14nm fin-based p-type metal-oxide-semiconductor field-effect transistors

A. Hikavyy, G. Mannaert, E. Rosseel, 2016 .

HF-Last Wet Clean in Combination with a Low Temperature GeH4-Assisted HCl In Situ Clean Prior to Si0.8Ge0.2-on-Si Epitaxial Growth

A. Hikavyy, K. Wostyn, B. Douhard, 2014 .

Towards high performance sub-10nm finW bulk FinFET technology

Naoto Horiguchi, Jérôme Mitard, P. Eyben, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

Trap Reduction and Performances Improvements Study after High Pressure Anneal Process on Single Crystal Channel 3D NAND Devices

A. Hikavyy, E. Rosseel, D. Linten, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, IEEE Transactions on Electron Devices.

Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster

A. Jourdain, G. Beyer, E. Beyne, 2021, 2021 Symposium on VLSI Technology.

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

J. Ryckaert, T. Chiarella, N. Horiguchi, 2020, 2020 IEEE Symposium on VLSI Technology.

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning

H. Mertens, A. Hikavyy, Z. Tao, 2023, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2022, 2022 International Electron Devices Meeting (IEDM).

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections

A. Jourdain, A. Hikavyy, G. Mannaert, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters

A. Hikavyy, G. Mannaert, E. Rosseel, 2020, 2020 IEEE Symposium on VLSI Technology.

Stress in Silicon–Germanium Nanowires: Layout Dependence and Imperfect Source/Drain Epitaxial Stressors

A. Hikavyy, A. De Keersgieter, N. Horiguchi, 2021, IEEE Transactions on Electron Devices.

Toward high-performance and reliable Ge channel devices for 2 nm node and beyond

A. Hikavyy, E. Rosseel, N. Horiguchi, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

(Invited) Stress Simulations of Fins, Wires, and Nanosheets

A. Hikavyy, A. De Keersgieter, N. Horiguchi, 2020, ECS Meeting Abstracts.

Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFET

A. Hikavyy, A. De Keersgieter, H. Bender, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Nanosheet-based Device Architectures with Front/Backside Connectivity: Opportunities for S/D Engineering to Enable Advanced CMOS Logic Scaling

A. Hikavyy, N. Horiguchi, A. Veloso, 2023, International Workshop on Junction Technology.

Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling

A. Jourdain, A. Hikavyy, N. Horiguchi, 2022, International Conference on IC Design & Technology.

Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond

F. M. Bufler, H. Mertens, R. Ritzenthaler, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

(Invited) Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts

A. Hikavyy, R. Loo, P. Favia, 2021, ECS Transactions.

SiGe band-to-band tunneling calibration based on p-i-n diodes: Fabrication, measurement and simulation

A. Hikavyy, H. Dekkers, B. Douhard, 2013 .

First Demonstration of SiGe Channel in Macaroni Geometry for Future 3D NAND

A. Hikavyy, F. Sebaai, E. Vecchio, 2017, 2017 IEEE International Memory Workshop (IMW).

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

L. Witters, N. Waldron, N. Collaert, 2013, 2013 IEEE International Electron Devices Meeting.

First demonstration of 15nm-WFIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain

H. Mertens, A. Hikavyy, H. Bender, 2014, 2014 IEEE International Electron Devices Meeting.

Factors Influencing the Leakage Current in Embedded SiGe Source/Drain Junctions

A. Hikavyy, H. Bender, R. Loo, 2008, IEEE Transactions on Electron Devices.