Z. Tao

发表

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE Symposium on VLSI Technology.

Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Christopher J. Wilson, B. T. Chan, H. Mertens, 2020, IEEE Transactions on Electron Devices.

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

B. Parvais, B. Kaczer, E. Simoen, 2016, 2016 IEEE Symposium on VLSI Technology.

Invited) Vertical Nanowire FET Integration and Device Aspects

Nadine Collaert, Aaron Thean, Tsvetan Ivanov, 2016 .

Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2021, 2021 Symposium on VLSI Technology.

Size Independent pH Sensitivity for Ion Sensitive FinFETs Down to 10 nm Width

Z. Tao, A. Veloso, L. Lagae, 2019, IEEE Sensors Journal.

12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices

D. Mocuta, J. Mitard, F. Masuoka, 2019, 2019 Symposium on VLSI Technology.

Vertical nanowire FET integration and device aspects

B. T. Chan, Z. Tao, E. Rosseel, 2016 .

Scaling of double-gated WS2 FETs to sub-5nm physical gate length fabricated in a 300mm FAB

H. Mertens, Z. Tao, T. Schram, 2021, International Electron Devices Meeting.

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

H. Mertens, R. Ritzenthaler, Z. Tao, 2020, 2020 IEEE Symposium on VLSI Technology.

Enabling 3D NAND Trench Cells for Scaled Flash Memories

M. Rosmeulen, Z. Tao, S. Ramesh, 2023, International Memory Workshop.

FEOL dry etch process challenges of ultimate FinFET scaling and next generation device architectures beyond N3

Zheng Tao, Boon Teik Chan, Liping Zhang, 2020, Advanced Lithography.

Middle-of-line plasma dry etch challenges for CFET integration

H. Mertens, Z. Tao, N. Horiguchi, 2023, Advanced Lithography.

Buried power rail integration for CMOS scaling beyond the 3 nm node

H. Mertens, Z. Tao, G. Mannaert, 2022, Advanced Lithography.

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

H. Mertens, Z. Tao, K. Devriendt, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning

H. Mertens, A. Hikavyy, Z. Tao, 2023, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Geert Hellings, Eddy Simoen, Niamh Waldron, 2017 .

Patterning challenges in advanced device architectures: FinFETs to nanowires

L. Witters, N. Waldron, N. Collaert, 2016, SPIE Advanced Lithography.

Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS

E. Simoen, G. Hellings, E. Vecchio, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM

Z. Tao, K. Devriendt, D. Mocuta, 2018, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).