S. Chew

发表

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE Symposium on VLSI Technology.

Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

S. Chew, T. Schram, K. Devriendt, 2014 .

Reliability in gate first and gate last ultra-thin-EOT gate stacks assessed with CV-eMSM BTI characterization

S. Chew, T. Schram, A. Veloso, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Improved sidewall doping of extensions by AsH3 ion assisted deposition and doping (IADD) with small implant angle for scaled NMOS Si bulk FinFETs

K. B. Noh, M. Kim, S. Chew, 2013, 2013 IEEE International Electron Devices Meeting.

A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies

E. Simoen, R. Ritzenthaler, N. Horiguchi, 2014, 2014 IEEE International Electron Devices Meeting.

Heterostructure at CMOS source/drain: Contributor or alleviator to the high access resistance problem?

A. Hikavyy, S. Chew, E. Rosseel, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Reliability Investigation of W2W Hybrid Bonding Interface: Breakdown Voltage and Leakage Mechanism

E. Beyne, S. Chew, K. Croes, 2022, 2022 IEEE International Reliability Physics Symposium (IRPS).

Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond

B. Parvais, A. Brand, N. Horiguchi, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

S. Chew, T. Schram, K. Devriendt, 2013 .

Process control & integration options of RMG technology for aggressively scaled devices

S. Chew, T. Schram, K. Devriendt, 2012, Symposium on VLSI Technology.

W versus Co–Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes

Tom Schram, Anabela Veloso, S. A. Chew, 2013 .

Titanium (germano-)silicides featuring 10−9 Ω·cm2 contact resistivity and improved compatibility to advanced CMOS technology

S. Chew, D. Mocuta, N. Horiguchi, 2018, 2018 18th International Workshop on Junction Technology (IWJT).

Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching $1 \times 10^{-9}$ Ohm-cm2

Naoto Horiguchi, Nadine Collaert, Daeyong Kim, 2016, IEEE Transactions on Electron Devices.

700nm pitch Cu/SiCN wafer-to-wafer hybrid bonding

Andy Miller, G. Beyer, E. Beyne, 2022, 2022 IEEE 24th Electronics Packaging Technology Conference (EPTC).

A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

Naoto Horiguchi, Wilfried Vandervorst, Tom Schram, 2014, IEEE Transactions on Electron Devices.

On the scalability of doped hafnia thin films

J. Woicik, S. Chew, T. Schram, 2014 .

Ultralow resistive wrap around contact to scaled FinFET devices by using ALD-Ti contact metal

A. Hikavyy, S. Chew, G. Mannaert, 2017, 2017 IEEE International Interconnect Technology Conference (IITC).

Process options to enable (sub-)1e-9 Ohm.cm2 contact resistivity on Si devices

S. Chew, E. Rosseel, S. Demuynck, 2016, 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).

Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation

A. Hikavyy, S. Chew, E. Rosseel, 2016, 2016 IEEE Symposium on VLSI Technology.

Replacement Metal Contact Using Sacrificial ILD0 for Wrap Around Contact in Scaled FinFET Technology

S. Chew, K. Devriendt, S. Demuynck, 2018, 2018 IEEE International Interconnect Technology Conference (IITC).

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

D. Mocuta, H. Bender, R. Ritzenthaler, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Towards high performance sub-10nm finW bulk FinFET technology

Naoto Horiguchi, Jérôme Mitard, P. Eyben, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

Highly scalable effective work function engineering approach for multi-VT modulation of planar and FinFET-based RMG high-k last devices for (Sub-)22nm nodes

E. Simoen, E. Vecchio, H. Bender, 2013, 2013 Symposium on VLSI Technology.

Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

Mattan Kamon, Jérôme Mitard, Tom Schram, 2020, IEEE Transactions on Electron Devices.

Diffusion and Gate Replacement: A New Gate-First High- $k$ /Metal Gate CMOS Integration Scheme Suppressing Gate Height Asymmetry

Naoto Horiguchi, Jerome Mitard, Eddy Simoen, 2016, IEEE Transactions on Electron Devices.

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

D. Mocuta, R. Ritzenthaler, W. Vandervorst, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).